PPC440EP-3JC533C Applied Micro Circuits Corporation, PPC440EP-3JC533C Datasheet - Page 15

• Manufacturer Part Number: PPC440EP-3JC533C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440EP-3JC533C

• Family Name: 440EP
• Device Core: PowerPC
• Device Core Size: 16b
• Frequency (max): 533MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.4/2.3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Lead Free Status / RoHS Status: Compliant

Serial Peripheral Interface (SPI/SCP)
The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous,
character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on
the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB.
Features include:
Universal Serial Bus (USB)
The USB interfaces provide both device and host support for version 1.1 and device support for version 2.0.
Support for the USB 2.0 Transceiver Macrocell Interface (UTMI) specification is included.
Features include:
NAND Flash Controller
The NAND Flash controller provides a simple interface between the EBC and up to four separate external NAND
Flash devices. It provides both direct command, address, and data access to the external device as well as a
memory-mapped linear region that generates data accesses. NAND Flash device data appears on the peripheral
data bus.
Features include:
AMCC Proprietary
440EP – PPC440EP Embedded Processor
• Three-wire serial port interface
• Full-duplex synchronous operation
• SCP bus master
• OPB bus slave
• Programmable clock rate divider
• Clock inversion
• Reverse data
• Local data loop back for test
• USB 1.1 Host port with internal PHY
• USB 2.0 Device UTMI or USB 1.1 Device PHY
• 1 to 4 banks supported on EBC
• Direct Interfacing to:
• Device sizes:
• (512 + 16)-B or (2K + 64)-B device page sizes supported
• Boot-from-NAND: Execute a linear sequence of boot code out of the first 4KB of block 0
• Support DMA to allow direct, no-processor-intervention block copy from NAND Flash to SDRAM
• ECC provides single-bit error correction and double-bit error detection in each 256B of stored data
• Chip selects shared with EBC
– Discrete NAND Flash devices (up to 4 devices)
– SmartMedia Card socket (22-pins)
– 4MB and larger supported for read/write access
– 4MB to 256MB for boot-from-NAND flash (size supported depends on addressing mode)
• Device support provides 6 end points (3 in, 3 out)
• 1024B FIFO (double buffering of 512B packets)
• FIFOs are not shared between in and out endpoints
• Endpoints do not support high-bandwidth isochronous transfers
• Two USB 2.0 device end points have DMA dedicated channels (DMA to PLB 128)
Revision 1.29 – May 07, 2008
Data Sheet
15