MCIMX515CJM6C Freescale, MCIMX515CJM6C Datasheet - Page 138
MCIMX515CJM6C
Manufacturer Part Number
MCIMX515CJM6C
Description
Manufacturer
Freescale
Datasheet
1.MCIMX515CJM6C.pdf
(200 pages)
Specifications of MCIMX515CJM6C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Electrical Characteristics
4.7.16
Table 106
4.7.16.1 UART Electrical
This section describes the electrical information of the UART module.
138
TXD_MUX
RXD_MUX
DCD
Port
CTS
DTR
DSR
RTS
RI
shows the UART I/O configuration based on which mode is enabled.
UART
•
•
•
•
•
Direction
Output
Output
Output
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Input
Input
Input
Input
Input
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
RTS from DTE to DCE
CTS from DCE to DTE
DTR from DTE to DCE
DSR from DCE to DTE
DCD from DCE to DTE
RING from DCE to DTE
Serial data from DCE to DTE
Serial data from DTE to DCE
Table 106. UART I/O Configuration vs. Mode
DTE Mode
Description
NOTE
Direction
Output
Output
Output
Output
Output
Input
Input
Input
RTS from DTE to DCE
CTS from DCE to DTE
DTR from DTE to DCE
DSR from DCE to DTE
DCD from DCE to DTE
RING from DCE to DTE
Serial data from DCE to DTE
Serial data from DTE to DCE
DCE Mode
Description
Freescale Semiconductor
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