MCIMX515CJM6C Freescale, MCIMX515CJM6C Datasheet - Page 76

• Manufacturer Part Number: MCIMX515CJM6C
• Manufacturer: Freescale

Specifications of MCIMX515CJM6C

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

1
Electrical Characteristics
4.7.4
This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC
is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver
interface and transceiver function are required to complete the interface to the media. The FEC supports
the 10/100 Mbps MII (18 pins in total) and the 10 Mbps-only 7-wire interface, which uses 7 of the MII
pins, for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, refer to the
i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM).
This section describes the AC timing specifications of the FEC.
4.7.4.1
The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must
exceed twice the FEC_RX_CLK frequency.
parameters and
76
1
2
3
4
5
.
Num
FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode.
SD7
SD8
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal speed mode for SD/SDIO card, clock frequency can be any value between 0
frequency can be any value between 0
In normal speed mode for MMC card, clock frequency can be any value between 0
frequency can be any value between 0
Measurement taken with CLoad = 20 pF
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
M1
M2
M3
M4
ID
eSDHC Input Setup Time
eSDHC Input Hold Time
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
FEC_RX_CLK pulse width high
FEC_RX_CLK pulse width low
FEC AC Timing Parameters
MII Receive Signal Timing
Figure 42
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Table 69. eSDHCv2 Interface Timing Specification (continued)
shows MII receive signal timings.
Parameter
Characteristic
–
–
Table 70. MII Receive Signal Timing
50 MHz.
52 MHz.
1
Table 70
lists the MII receive channel signal timing
Symbols
t
t
ISU
IH
5
35%
35%
Min
5
5
–
20 MHz. In high-speed mode, clock
–
25 MHz. In high-speed mode, clock
Min
2.5
2.5
Max
65%
65%
—
—
Freescale Semiconductor
FEC_RX_CLK period
FEC_RX_CLK period
Max
—
—
Unit
ns
ns
Unit
ns
ns