MCIMX515CJM6C Freescale, MCIMX515CJM6C Datasheet - Page 24

• Manufacturer Part Number: MCIMX515CJM6C
• Manufacturer: Freescale

Specifications of MCIMX515CJM6C

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics
4.2.1
Figure 2
4.3
This section includes the DC parameters of the following I/O types:
24
1. VDD_FUSE should only be powered when writing.
2. NVCC_PERx refers to NVCC_PER 3, 5, 8, 9, 10, 11, 12, 13, 14.
3. No power-up sequence dependencies exist between the supplies shown in the block diagram shaded in gray.
4. There is no requirement for VDDGP to be preceded by any other power supply other than NVCC_SRTC_POW.
5. If all of the UHVIO supplies (NVCC_NANDFx, NVCC_PER15 and NVCC_PER17) are less than 2.75 V then there is no
requirement on the power up sequence order between NVCC_EMI_DRAM and the UHVIO supplies. However, if the voltage
is 2.75 V and above, then NVCC_EMI_DRAM needs to power up before the UHVIO supplies as shown here.
NVCC_EMI_DRAM
•
•
•
•
•
•
NVCC_SRTC_POW
NVCC_NANDF_x
NVCC_PER15
NVCC_PER17
General Purpose I/O and High-Speed General Purpose I/O (GPIO/HSGPIO)
Double Data Rate 2 (DDR2)
Low Voltage I/O (LVIO)
Ultra High Voltage I/O (UHVIO)
High-Speed I
Enhanced Secure Digital Host Controller (eSDHC)
shows the power-up sequence.
I/O DC Parameters
Power-Up Sequence
VCC
The POR_B input must be immediately asserted at power-up and remain
asserted until after the last power rail is at its working voltage.
For more information on power up, see i.MX51 Power-Up Sequence
(AN4053)i.MX51
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
2
C and I
VDDA
2
VDDGP
C
4
Figure 2. Power-Up Sequence
NVCC_HS4_1
NVCC_HS4_2
NVCC_PERx
NVCC_HS10
NVCC_HS6
NVCC_EMI
NVCC_IPU
NVCC_I2C
NOTE
2
VDD_ANA_PLL_A/B
VDD_DIG_PLL_A/B
NVCC_TV_BACK
TVDAC_DHVDD
NVCC_USBPHY
AHVDDRGB
NVCC_OSC
VDDA33
Freescale Semiconductor
VDD_FUSE
1