MCIMX515CJM6C Freescale, MCIMX515CJM6C Datasheet - Page 64

• Manufacturer Part Number: MCIMX515CJM6C
• Manufacturer: Freescale

Specifications of MCIMX515CJM6C

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics
Figure 32
diagram is shown in
1
2
3
64
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for
address and controls.
SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock).
This parameter is affected by pad timing. If the slew rate is < 1 V/ns, 0.1 ns should be increased to this value.
DD17
DD18
DD19
DD20
DD21
DD22
DD23
ID
DQM (output)
DQS (output)
DQ (output)
shows the timing diagram for mDDR SDRAM write cycle. The timing parameters for this
DQ and DQM setup time to DQS
DQ and DQM hold time to DQS
Write cycle DQS falling edge to
SDCLK output setup time
Write cycle DQS falling edge to
SDCLK output hold time
Write command to first DQS latching
transition
DQS high level width
DQS low level width
SDCLK_B
SDCLK
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Table
Parameter
Table 56. mDDR SDRAM Write Cycle Parameter Table
Figure 32. mDDR SDRAM Write cycle Timing Diagram
56.
DD21
DD17
DD17
Data
DM
DD18
DD18
Symbol
Data
DM
t
t
t
t
DQSS
DQSH
t
t
t
DQSL
DSH
DS
DH
DSS
3
1
Data
DM
DD17
0.48
0.48
0.75
DD22
DD17
Min
0.2
0.2
0.4
0.4
200 MHz
Data
DM
Max
1.25
0.6
0.6
DD23
—
—
—
—
2
DD18
DD18
Data
DM
0.75
Min
0.6
0.6
0.2
0.2
0.4
0.4
166 MHz
Data
DM
Max
1.25
DD19
0.6
0.6
1
—
—
—
—
Data
DM
Freescale Semiconductor
0.75
Min
0.8
0.8
0.2
0.2
0.4
0.4
133 MHz
Data
DM
Max
1.25
0.6
0.6
—
—
—
—
DD20
Unit
tCK
tCK
tCK
tCK
tCK
ns
ns