MCIMX515CJM6C Freescale, MCIMX515CJM6C Datasheet - Page 94
MCIMX515CJM6C
Manufacturer Part Number
MCIMX515CJM6C
Description
Manufacturer
Freescale
Datasheet
1.MCIMX515CJM6C.pdf
(200 pages)
Specifications of MCIMX515CJM6C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Electrical Characteristics
4.7.8.6
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of
the interface is described in
94
2
3
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
Display interface clock down time
Display interface clock up time
Interface to a TV Encoder
•
•
•
•
•
•
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
The frequency of the clock DISP_CLK is 27 MHz (within 10%)
The HSYNC, VSYNC signals are active low.
The DRDY signal is shown as active high.
The transition to the next row is marked by the negative edge of the
HSYNC signal. It remains low for a single clock cycle
The transition to the next field/frame is marked by the negative edge of
the VSYNC signal. It remains low for at least one clock cycles
—
of VSYNC and HSYNC coincide.
—
coincide.
The active intervals—during which data is transferred—are marked by
the HSYNC signal being high.
At a transition to an odd field (of the next frame), the negative edges
At a transition is to an even field (of the same frame), they do not
Figure
Tdicd
Tdicu
56.
=
=
1
-- - T diclk
2
⎛
⎝
1
-- - T diclk
2
⎛
⎝
×
ceil
×
NOTE
ceil
2
------------------------------------------------------------ -
×
2
-------------------------------------------------- -
DI_CLK_PERIOD
DI_CLK_PERIOD
DISP_CLK_DOWN
×
DISP_CLK_UP
⎞
⎠
⎞
⎠
Freescale Semiconductor
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