PNX1700EH/G,557 Trident Microsystems, Inc., PNX1700EH/G,557 Datasheet - Page 121

• Manufacturer Part Number: PNX1700EH/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of PNX1700EH/G,557

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Volume 1 of 1
Table 4: Semaphore MMIO Registers
6. System Related Information for TM5250
Table 5: Interrupt Source Assignments
PNX17XX_SER_1
Preliminary data sheet
31:0
Offset 0x06 383C
31:0
SOURCE NAME
PCI_INTA_N
PCI_GNT_A_N
PCI_GNT_B_N
PCI_REQ_A_N
PCI_REQ_B_N
TIMER1
TIMER2
Bits
Symbol
SEMAPHORE14
SEMAPHORE15
6.1 Interrupts
SOURCE
NUMBER
0
1
2
3
4
5
6
SEMAPHORE15
This section contains information on how the internal TM5250 resources like its
interrupt lines or timers have been assigned or used in the PNX17xx Series system.
More specific details on how to program or on the exact behavior of these resources
is found in [1].
A fundamental aspect of PNX17xx Series system is to provide hardware modules (or
hardware accelerators) that relieve the TM5250 CPU for other video/audio
processing. These modules are mainly internal bus DMA masters. Thus once
programmed by the TM5250 they only require limited CPU processing power. For
example the video module only requires the TM5250 to update the pointers to the
next frame 60 times per seconds. An interrupt line is used to signal TM5250 of that
need.
The TM5250 Vectored Interrupt Controller (VIC) provides 64 inputs for interrupt
request lines. The interrupt controller prioritizes and maps the multiple requests from
the several PNX17xx Series modules onto successive interrupt requests to the
TM5250 execution unit.
Table 5
recommended operating mode (edge or level triggered). Note that there are a total of
7 possible external pins to assert interrupt requests. Only PCI_INTA_N is a dedicated
pin for external interrupts. The other pins may be used for other functionality. The first
5 interrupt sources, i.e. source 0 through 4, are asserted by active low signal
conventions, i.e. a zero level or a negative edge asserts a request. The remaining two
external interrupt lines, i.e. source 26 and 27, like all the other regular interrupt lines,
operate with active high signalling conventions.
Acces
s
R/W
R/W
INTERRUPT
OPERATING MODE
level
level
level
level
level
edge
edge
shows the assignment of modules to interrupt source numbers, as well as the
…Continued
Value
0
0
Rev. 1 — 17 March 2006
Description
Same as semaphore0 register.
Same as semaphore0 register.
SOURCE DESCRIPTION
External PCI INTA interrupt used by the host CPU. Active
LOW
Direct external interrupt input line, active LOW
Direct external interrupt input line, active LOW
Direct external interrupt input line, active LOW
Direct external interrupt input line, active LOW
General purpose internal TM5250 timer
General purpose internal TM5250 timer
Chapter 3: System On Chip Resources
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
3-12