PNX1700EH/G,557 Trident Microsystems, Inc., PNX1700EH/G,557 Datasheet - Page 78

• Manufacturer Part Number: PNX1700EH/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of PNX1700EH/G,557

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
10.3.1 Do DDR Devices Require Termination?
10.3.2 What if I really want to use termination for the PNX17xx Series?
Table 43: DDR Recommended Trance Length
The ball assignment implies that the two outside rows of balls are routed on a
different board layer than the next two rows of balls. This is recommended to reduce
the skew. The DQS lines are the exception since they are located on the outside row
for better package signal integrity.
A 10-22
placed as close as possible to the PNX1700 clock output pins. In addition a 100
shunting both memory clocks, i.e. MM_CLK and MM_CLK#, will reduce the swing of
the signals and improve signal integrity. The 100
devices.
No other termination is required at board level to achieve maximum speed if these
rules are strictly followed.
Above DDR333, i.e. MM_CLK of 166 MHz, the 183 or 200 MHz operating speeds (i.e.
DDR400) are only available for a maximum of 2 loads.
VREF, a.k.a. AVREF, can be generated by using a simple voltage resistor divider. 100
one local VREF for PNX1700 and one local VREF for the DDRs is slightly better.
Most DDR devices are meant to drive very long and highly loaded track lines. Their
drivers are usually very strong and could use a 22
and dqs lines on the DDR device’s end.
It is possible to parallel terminate each line to a termination voltage with a 50
resistor to avoid over-undershoots and therefore potential too high EMC/EMI noise.
The resistor should be placed as close as possible to the intersection of the leg of ‘T’
and the bar of the ‘T’ (this applies when the signal has two or more loads). For single
loaded tracks and bi-directional signals, the parallel termination resistor should be
placed about 50% of the way to the DDR SDRAM device. For unidirectional signals
and single loaded tracks, the termination should be placed after the pin of DDR
SDRAM device. In this case, the VTT supply must be carefully designed with very
wide tracks since the current through that power supply is very high due to the
termination and its active current consumption over 80+ pins. The VTT power island
Signal
MM_CK, MM_CK#
MM_AD[12:0], MM_BA[1:0]
MM_RAS/CAS/WE/CKE
MM_CS[1:0]
MM_DQS[3:0]
MM_DATA[31:0]
MM_DQM[3:0]
•
to 150
Recommended Trace lengths for operating frequency of up to DDR400 are
shown in
series resistor is recommended on the two clock lines. They need to be
1% resistors are recommended. VREF should be on a wide trace. Having
Table
Rev. 1 — 17 March 2006
43.
Maximum (cm)
4
7
2
3
Chapter 1: Integrated Circuit Data
can be placed after the DDR
series resistors on the data/dqm
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Minimum (cm)
4
4
2
1
PNX17xx Series
1-51