PNX1700EH/G,557 Trident Microsystems, Inc., PNX1700EH/G,557 Datasheet - Page 282

• Manufacturer Part Number: PNX1700EH/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of PNX1700EH/G,557

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 5:
Up to 4-bit Signal Sampling
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
31
31
31
IO_SEL_3 sample IO_SEL_2 sample IO_SEL_1 sample IO_SEL_0 sample
IO_SEL_0 sample
IO_SEL_1 sample IO_SEL_0 sample
15
2.3.2 The Signal Pattern Generation Mode
7
14
31
31
31
13
buffer. The numbers of signals to sample together per FIFO queue is programmed by
setting the GPIO_EV[3:0].EN_IO_SEL fields. The signal selection for sampling is
programmed in the IO_SEL[3:0] registers.
The signal pattern generation mode is the dual of the signal sampling mode. The
software builds in memory DMA buffers that are fetched by the GPIO module. The
data is then transferred to a selected group of GPIO pins. Similarly to the sampling
mode the pattern generation mode offers two different ways to output signals:
Pattern generation can start once the software has filled the DMA buffers.
GPIO MMIO Description for Pattern Generation FIFO queues
The FIFO queues are controlled by the GPIO_EV[3:0] MMIO registers. The status of
the sampling and the interrupt control MMIO registers are INT_STATUS[3:0],
INT_ENABLE[3:0] and INT_CLEAR[3:0]. INT_SET[3:0] is only meant for software
debug (used to trigger the hardware interrupt but using software). In the following text
a ‘x’ may be used to refer to one of the 4 MMIO registers, e.g. GPIO_EVx or one of
the two flags, like BUFx_RDY for BUF2_RDY or BUF2_RDY.
Upon reset, transmission is disabled (GPIO_EVx.FIFO_MODE and
GPIO_EVx.EVENT_MODE is reset to 00), and the DMA buffer 1 is the active buffer.
The system software initiates transmission by providing two DMA buffers containing
6
•
•
12
Timestamp mode: The software creates DMA buffers that contain 32-bit values
as defined in
used to drive the GPIO pins with the correct polarity and to emit the sample at the
correct time, i.e. when the software computed timestamped matches the internal
timestamp counter.
Pattern mode: The GPIO module outputs the DMA buffer content on a select
group of GPIO pins. In this mode up to 4 signals per FIFO can be grouped for
pattern generation.
11
5
10
30
30
9
4
Section
Rev. 1 — 17 March 2006
8
7
3
2.2.2. The direction bit and the timestamp information is
6
29
5
2
Chapter 8: General Purpose Input Output Pins
4
3
1
2
28
1
0
0
0
0
0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
1-bit shifted in
=> 32 samples
2-bit shifted in
=> 16 samples
4-bits shifted in
=> 8 samples
8-11