PNX1700EH/G,557 Trident Microsystems, Inc., PNX1700EH/G,557 Datasheet - Page 124

• Manufacturer Part Number: PNX1700EH/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of PNX1700EH/G,557

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
6.3 System Parameters for TM5250
Table 6: TM5250 Timer Source Selection
Few more control parameters are available to tune the use of TM5250 and PNX17xx
Series. The MMIO register layout and offsets are described in
Remark: It is not recommended to have the TM5250 to flip itself to ‘1’ the
TM32_PWRDWN_REQ bit.
SOURCE NAME
GPIO_TIMER0
GPIO_TIMER1
REFERENCE_CLOCK
•
•
•
•
•
The CPU apertures (DRAM and APERT1 described in
modified by the TM5250 itself, if the TM32_APERT_MODIFIABLE bit is set to ‘1’.
In host mode the host CPU can decide to prevent TM5250 to go out of its allowed
apertures by flipping to ‘0’ the bit TM32_APERT_MODIFIABLE.
The TM32_LS_DBLLINE parameter may influence the overall performance of the
TM5250. This parameter is related to the cache line sizes and the optimal L2
Dcache burst than can be obtained. The default value favors the L1 to L2
bandwidth usage and improves slightly, in most cases, the TM5250 processing
power. However some applications may require a shorter memory burst to reduce
the bandwidth usage or to avoid some pathological cache trashing cases.
TM32_LS_DBLLINE can then be flipped to ‘0’. There is no available formula to
know if a particular application benefits from one setting or the other.
Experimentation on the final application is recommended to determine the
optimal settings. Note however that compared to the PNX15xx Series, TM5250
includes dedicated data prefetching hardware that significantly reduces data
cache stalls [1].
tm_5250_noal_allowed is connected to ‘1’ which always allows unaligned loads
[1].
tm_5250_debug_not_allowed is always connected to ‘0’ which makes all TM5250
MMIO registers visible from the HOST processor (if any).
It is possible for a host CPU to shutdown entirely the high speed clock of the
TM5250. The safe procedure consists in first requesting the TM5250 to prepare
itself for major powerdown mode. The host CPU needs first to alert the software
running on the TM5250 that a powerdown sequence is coming. The TM5250
software acknowledges that it is ready. Then the host CPU toggles the
TM32_PWRDWN_REQ bit to inform the TM5250 module that a full powerdown
mode is requested. The TM5250 hardware state machine replies by asserting the
TM32_PWRDWN_ACK bit. From this point TM5250 will not answer to any
request and its high speed CPU clock can be turned off by the CPU host. The
wake-up sequence starts by turning back on the high speed CPU clock and then
flip to ‘0’ the TM32_PWRDWN_REQ bit.
Rev. 1 — 17 March 2006
SOURCE NUMBER
13
14
15
Chapter 3: System On Chip Resources
SOURCE DESCRIPTION
GPIO pin selection 0
GPIO pin selection 1
The 27 MHz input crystal clock
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Section
Section
2.2) can be
6.3.1.
3-15