PNX1700EH/G,557 Trident Microsystems, Inc., PNX1700EH/G,557 Datasheet - Page 188

• Manufacturer Part Number: PNX1700EH/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of PNX1700EH/G,557

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX17XX_SER_1
Preliminary data sheet
Bit
Offset 0x04,701C
31
30:0
Offset 0x04,7020
31
30:0
Offset 0x04,7024
31
30:0
Offset 0x04,7028
31
30:0
Offset 0x04,702C
31
30:0
Offset 0x04,7030
31
30:0
Divider Registers:
Offset 0x04,7034
31:8
8
7
6
5
4
3
Symbol
Enable
dds3_ctl[30:0]
Enable
dds4_ctl[30:0]
Enable
dds5_ctl[30:0]
Enable
dds6_ctl[30:0]
Enable
dds7_ctl[30:0]
Enable
dds8_ctl[30:0]
Reserved
pd_192
pd_173
pd_157
pd_144
pd_133
pd_123
For register 34h power down appropriate clocks before setting these bits
DDS3_CTL
DD4_CTL
DDS5_CTL
DDS6_CTL
DDS7_CTL
DDS8_CTL
CAB_DIVIDER_CTL
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
…Continued
Value
0
0x02F68
4C0
0
0x02F68
4C0
0
0x00E90
452
0
0x04000
000
0
0x04000
000
0
0x04000
000
0
0
0
0
0
0
Rev. 1 — 17 March 2006
Description
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS3 control (default = 20 MHz)
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS4 control (default = 20 MHz)
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS5 control (default = 128*48kHz = 6.14 MHz)
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS6 control (default = 27 MHz)
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS7 control (default = 27 MHz)
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS8 control (default = 27 MHz)
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Power down 192 MHz divider in the CAB block.
Power down 173 MHz divider in the CAB block.
Power down 157 MHz divider in the CAB block. Must be set to ‘1’
then ‘0’ before using clk_157 or its derivatives.
Power down 144 MHz divider in the CAB block.
Power down 133 MHz divider in the CAB block. Must be set to ‘1’
then ‘0’ before using clk_133 or its derivatives.
Power down 123 MHz divider in the CAB block.
MUST BE INITIALIZED BEFORE BEING USED.
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
5-37