PNX1700EH/G,557 Trident Microsystems, Inc., PNX1700EH/G,557 Datasheet - Page 268

• Manufacturer Part Number: PNX1700EH/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of PNX1700EH/G,557

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Volume 1 of 1
Table 10: PCI Configuration Registers
PNX17XX_SER_1
Preliminary data sheet
Bit
7:0
Offset 0x000C
31:16
15:8
7:0
Offset 0x0010
This aperture is for the SDRAM on the PNX17xx Series.
31:28
27:21
20:4
3
2:0
Offset 0x0014
This aperture will be set to 2 MB for MMIO on the PNX17xx Series.
31:28
27:21
20:4
3
Symbol
Revision ID
Reserved
Latency Timer
Cache Line Size
Base10 Address
Base10 Address
Reserved
Prefetchable
Type
Base14 Address
Base14 Address
Reserved
Prefetchable
Latency Timer/Cache Line Size
Base10 Address Register
Base14 Address Register
Acces
s
R
R
R/W
R/W
R/W
R/W*
R
R
R
R/W
R/W*
R
R
Value
1
0x0000
0
0
0
0
0
*cfg
0
0001
1011111
0
*cfg
Rev. 1 — 17 March 2006
Description
Revision ID. Will initially be assigned to 0. Revision ID must not be
synthesized. It will need to be changed with revised silicon, whether
for bug fixes or enhancements.
Note: BIST is not implemented. Header is 0.
Latency Timer
Cache Line Size
Upper 4 bits of base10 address of the first memory aperture
*The base 10 can be configured to various aperture sizes from 2
MB to 256 MB. (See pci_setup register). Depending on aperture
size selected, various bits will be R/W or Read Only.
Bit:
256M: RO
128M: RW
64M:
32M:
16M:
8M:
4M:
2M:
RO = Read-only bits read back as zero.
Value is determined at boot time by the pci_setup register.
Indicates type 0 memory space (locatable anywhere in 32-bit
address space).
Upper 4 bits of base14 address of the first memory or IO aperture
*The base 14 can be configured to various aperture sizes from 2
MB to 256 MB. (See pci_setup register). Depending on aperture
size selected, various bits will be R/W or Read Only.
Bit:
256M:
128M:
64M:
32M:
16M:
8M:
4M:
2M:
RO = Read-only bits read back as zero.
Value is determined at boot time by the pci_setup register.
27
RW
RW
RW
RW
RW
RW
27
RO
RW
RW
RW
RW
RW
RW
RW
26
RO
RO
RW
RW
RW
RW
RW
RW
26
RO
RO
RW
RW
RW
RW
RW
RW
25
RO
RO
RO
RW
RW
RW
RW
RW
25
RO
RO
RO
RW
RW
RW
RW
RW
24
RO
RO
RO
RO
RW
RW
RW
RW
24
RO
RO
RO
RO
RW
RW
RW
RW
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
23
RO
RO
RO
RO
RO
RW
RW
RW
23
RO
RO
RO
RO
RO
RW
RW
RW
Chapter 7: PCI-XIO Module
PNX17xx Series
22
RO
RO
RO
RO
RO
RO
RW
RW
22
RO
RO
RO
RO
RO
RO
RW
RW
21
RO
RO
RO
RO
RO
RO
RO
RW
21
RO
RO
RO
RO
RO
RO
RO
RW
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