SAA7144 NXP Semiconductors, SAA7144 Datasheet - Page 20

• Manufacturer Part Number: SAA7144
• Manufacturer: NXP Semiconductors

Specifications of SAA7144

• Package Type: LQFP
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 14454
Product data sheet
Fig 17. Luminance and sync processing (continued from
SCL_AB
This is valid for decoder A, B, C and D. Here an example for decoder A is shown.
INTERFACE
PREFILTER
PREFILTER
CONTROL
I
I
2
2
SYNC
46
C-BUS
C-BUS
LUM
8.5 Synchronization
PREF
SDA_AB
47
SYNCHRONIZATION CIRCUIT
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is
further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the
phase detectors where they are compared with the sub-divided clock frequency. The
resulting output signal is applied to the loop filter to accumulate all phase deviations.
Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end
requirements. The loop filter signal drives an oscillator to generate the line frequency
control signal LFCO; see
The detection of ‘pseudo syncs’ as part of the Macrovision
also achieved within the synchronization circuit.
The result is reported as flag COPRO within the decoder status byte at subaddress 1Fh.
VNOI[1:0]
HTC[1:0]
MACROVISION
PROCESSOR
DETECTOR
SLICER
VERTICAL
CHROMINANCE
SYNC
BYPS
VBLB
TRAP
FIDT
LUMINANCE CIRCUIT
HSB[7:0]
HSS[7:0]
AUFD
COPRO
FSEL
COUNTER
DETECTOR
PHASE
FINE
HLCK
BAND-PASS
Rev. 01 — 21 April 2005
VARIABLE
BPSS[1:0]
FILTER
Figure
PREF
HTC[1:0]
HPLL
DETECTOR
MATCHING
AMPLIFIER
COARSE
FILTER
PHASE
18.
LOOP
VBLB
Figure
HTC[1:0]
APER[1:0]
AND ADDING
WEIGHTING
VBLB
STAGE
10).
Y
OSCILLATOR
DISCRETE
TIME
DAC
CLOCK CIRCUIT
Quadruple video input processor
®
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
copy protection standard is
LINE-LOCKED
GENERATION
GENERATOR
GENERATOR
CRYSTAL
CLOCKS
CIRCUIT
CLOCK
CLOCK
CLOCK
SAA7144HL
001aab309
104
85
80
84
81
LLC_A
V
V
XTALI
XTALO
DDDA
SSDA
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