SAA7144 NXP Semiconductors, SAA7144 Datasheet - Page 23

• Manufacturer Part Number: SAA7144
• Manufacturer: NXP Semiconductors

Specifications of SAA7144

• Package Type: LQFP
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 14454
Product data sheet
8.8 Multistandard VBI data slicer
8.9 VBI-raw data bypass
The multistandard data slicer is a Vertical Blanking Interval (VBI) and Full Field (FF) video
data acquisition block. In combination with software modules the slicer acquires most
existing formats of broadcast VBI and FF data.
The implementation and programming model is in accordance with the VBI data slicer
built into the multimedia video data acquisition circuit SAA5284.
The circuitry recovers the actual clock phase during the clock run-in period, slices the data
bits with the selected data rate, and groups them into bytes. The clock frequency, signal
source, field frequency and accepted error count must be defined via the I
subaddress 40h, bits 7 to 4.
Several standards can be selected per VBI line. The supported VBI data standards are
described in
The programming of the desired standards is done via I
(LCR2[7:0] to LCR24[7:0]); see detailed description in
processing to the signals source, there are offsets in horizontal and vertical direction
available via the I
5Bh (bit 4), 5Ah (VOFF8 to VOFF0). The formatting of the decoded VBI data is done
within the output interface to the VPO-bus. For a detailed description of the sliced data
format see
Table 6:
For a 27 MHz VBI-raw data bypass the digitized CVBS signal is upsampled after
analog-to-digital conversion. Suppressing of the back folded CVBS frequency
components after upsampling is achieved by an interpolation filter; see
Standard type
Teletext EuroWST,
CCST
European closed
caption
VPS
Wide screen signalling
bits
US teletext (WST)
US closed caption
(line 21)
Teletext
VITC/EBU time codes
(Europe)
VITC/SMPTE time
codes (USA)
US NABTS
MOJI (Japanese)
Japanese format
switch (L20/22)
Supported VBI standards
Table
Table
2
20.
C-bus in subaddresses 5Bh (bits 2 to 0), 59h (HOFF10 to HOFF0) and
6.
Data rate (Mbit/s) Framing code
6.9375
0.500
5
5
5.7272
0.503
6.9375
1.8125
1.7898
5.7272
5.7272
5
Rev. 01 — 21 April 2005
27h
001
9951h
1E3C1Fh
27h
001
programmable
programmable
programmable
programmable
programmable (A7h) Japtext
programmable
Quadruple video input processor
Section
2
C-bus subaddresses 41h to 57h
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
FC window Hamming check
WST625
CC625
VPS
WSS
WST525
CC525
general text optional
VITC625
VITC625
NABTS
8.10. To adjust the slicers
SAA7144HL
Figure
always
always
optional
2
C-bus in
20.
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