DM74AS280MX_NL Fairchild Semiconductor, DM74AS280MX_NL Datasheet - Page 4

• Manufacturer Part Number: DM74AS280MX_NL
• Manufacturer: Fairchild Semiconductor

Specifications of DM74AS280MX_NL

• Logical Function: Parity Gen/Checker
• Logic Family: AS
• Number Of Elements: 1
• Number Of Bits: 9
• Propagation Delay Time: 12ns
• High Level Output Current: -2mA
• Low Level Output Current: 20mA
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC N
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Pin Count: 14
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Technology: Bipolar
• Lead Free Status / RoHS Status: Compliant

©1986 Fairchild Semiconductor Corporation
DM74AS280 Rev. 1.2
Switching Characteristics
Over recommended operating free air temperature range.
Typical Applications
Three DM74AS280s can be used to implement a 25-line
parity generator/checker.
As an alternative, the outputs of two or three parity
generators/checkers can be decoded with a 2-input
(AS86) or 3-input (S135) exclusive-OR gate for 18 or
27-line parity applications.
Figure 1. 25-Line Parity/Generator
Symbol
t
t
t
t
PLH
PHL
PLH
PHL
Checker
Propagation Delay Time,
LOW-to-HIGH Level Output
Propagation Delay Time,
HIGH-to-LOW Level Output
Propagation Delay Time,
LOW-to-HIGH Level Output
Propagation Delay Time,
HIGH-to-LOW Level Output
Parameter
V
C
R
CC
L
L
Conditions
50pF,
500
4.5V to 5.5V,
4
Figure 2. 81-Line Parity/Generator Checker
Longer word lengths can be implemented by cascading
DM74AS280s. As shown in Figure 2, parity can be
generated for word lengths up to 81 bits.
From
Data
Data
Even
To
Odd
Min.
3
3
3
3
Max.
11.5
12
11
12
www.fairchildsemi.com
Units
ns
ns
ns
ns