SSTUB32866BHLF IDT, Integrated Device Technology Inc, SSTUB32866BHLF Datasheet - Page 13

• Manufacturer Part Number: SSTUB32866BHLF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTUB32866BHLF

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

2. Device standard (cont'd)
1165A—3/21/07
†
‡
Figure 12 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in
(not used)
D1•D14 †
PAR_IN †
Q1•Q14
After RST is switched from low to high, all data and PAIR_IN inputs signals must be set and held low for a minimum time of t
max, to avoid false error
If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on
the n+2 clock pulse.
QERR# ‡
PPO
DCS
CSR
RST
CK
CK
t act
pair; C0=0, C1=1; RST switches from L to H
t pdm , t pdmss
n
t su
H, L, or X
CK to QERR
CK to Q
Data to QERR#
t PHL
Latency
13
n + 1
t su
t h
n + 2
CK to PPO
Advance Information
t h
t pd
H or L
ICSSSTUB32866B
n + 3
t PHL , t PLH
CK to QERR
n + 4
ACT