SSTUB32866BHLF IDT, Integrated Device Technology Inc, SSTUB32866BHLF Datasheet - Page 22

• Manufacturer Part Number: SSTUB32866BHLF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTUB32866BHLF

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

1165A—3/21/07
(over recommended operating free-air temperature range, unless otherwise noted)
Notes:
(over recommended operating free-air temperature range, unless otherwise noted)
2. Guaranteed by design, not 100% tested in production.
Timing Requirements
SYMBOL
Switching Characteristics
Symbol
t
t
f
fmax
PDMSS
INACT
t
t
t
t
t
clock
t
t
t
t
t
t
ACT
PDM
t
t
t
PHL
PHL
PLH
PD
su
su
su
su
LH
HL
W
H
Clock frequency
Pulse duration, CK, CK HIGH or LOW
Differential inputs active time (See Notes 1 and 2)
Differential inputs inactive time (See Notes 1 and 3)
Setup time
Setup time
Setup time
Setup time
Hold time
Hold time
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CLK/ CLK signal input slew rate of 1V/ns.
Max input clock frequency
Propagation delay, single
bit switching
Propagation delay
Low to High propagation
delay
High to low propagation
delay
Propagation delay
simultaneous switching
High to low propagation
delay
High to low propagation
delay
Low to High propagation
delay
Parameter
PARAMETERS
CK↑ to CK↓ QN
CK↑ to CK↓ to PPO
CK↑ to CK ↓ to QERR
CK↑ to CK↓ QN
RESET ↓ to QN↓
RESET ↓ to PPO↓
RESET ↓ to QERR ↑
Measurement
Conditions
22
MIN
410
1.1
0.5
1.2
DCS before CK↑, CK ↓,
CSR high; CSR before CK↑,
CK↓, DCS high
DCS before CK↑, CK ↓,
CSR low
DODT, DCKE and data before
CK↑, CK ↓
PAR_IN before CK↑, CK ↓
DCS , DODT, DCKE and Q
after CK↑, CK ↓
PAR_IN after CK↑, CK ↓
1
-
MAX
1.9
1.8
2.4
3
2
3
3
3
Advance Information
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ICSSSTUB32866B
V
DD
MIN
0.8
0.5
0.5
0.5
0.4
0.4
1
= 1.8V ±0.1V
MAX
410
10
15
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns