74SSTUBF32868ABKG IDT, Integrated Device Technology Inc, 74SSTUBF32868ABKG Datasheet - Page 10

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74SSTUBF32868ABKG

Manufacturer Part Number
74SSTUBF32868ABKG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 74SSTUBF32868ABKG

Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Bits
28
Number Of Inputs
28
Number Of Outputs
56
High Level Output Current
-6mA
Low Level Output Current
6mA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Invert/Non-Invert
Technology
CMOS
Frequency (max)
410(Min)MHz
Mounting
Surface Mount
Pin Count
176
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
TI
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Part Number:
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Manufacturer:
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Absolute Maximum Ratings
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
IDT74SSTUBF32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range
Supply Voltage, V
Input Voltage Range, V
Output Voltage Range, V
Input Clamp Current, I
Output Clamp Current, I
Continuous Output Clamp Current, I
Continuous Current through each V
Package Thermal Impedance (
Storage Temperature, T
Parameter
dV/dt_r
dV/dt_f
dV/dt_∆
1
O/P clamp current are observed.
2
3
1
The input and output negative voltage ratings may be exceeded if the ratings of the I/P and
This current will flow only when the output is in the high state level V
The package thermal impedance is calculated in accordance with JESD 51.
Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
1
DD
IK
I
1
STG
OK
O 1,2
Item
θ
ja)
3
DD
O
or GND
0m/s Airflow
1m/s Airflow
10
V
Min.
DD
1
1
= 1.8V ± 0.1V
-0.5V to 2.5V
-0.5V to V
-0.5V to V
±50mA
±50mA
±50mA
±100mA
40.4° C/W
29.1° C/W
-65 to +150° C
Max.
DD
DDQ
4
4
1
COMMERCIAL TEMPERATURE GRADE
O
+ 2.5V
+ 0.5V
> V
Rating
DDQ
Units
V/ns
V/ns
V/ns
IDT74SSTUBF32868A
.
7068/10

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