74SSTUBF32868ABKG IDT, Integrated Device Technology Inc, 74SSTUBF32868ABKG Datasheet - Page 11

• Manufacturer Part Number: 74SSTUBF32868ABKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 74SSTUBF32868ABKG

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 28
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -6mA
• Low Level Output Current: 6mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Invert/Non-Invert
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 176
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
IDT74SSTUBF32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Terminal Functions
Terminal Name
QODT0, QODT1
DODT0, DODT1
QCKE0, QCKE1
DCKE0, DCKE1
QCS0, QCS1
DCS0, DCS1
Q1 - Q28
D1 - D28
CSGEN
PAR_IN
RESET
QERR
GND
V
CLK
CLK
V
NC
REV
C
DD
Open Drain Output
Characteristics
Differential Input
Differential Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
LVCMOS Input
LVCMOS Input
LVCMOS Input
Ground Input
1.8V nominal
0.9V nominal
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
Electrical
Ground
Power Supply Voltage
Input Reference Clock
Positive Master Clock Input
Negative Master Clock Input
Configuration Control Inputs - Register A or Register B
Asynchronous Reset Input. Resets registers and disables Vref data
and clock differential-input receivers.
Chip select gate enable – When high, D1-D28 inputs will be latched
only when at least one chip select input is low during the rising edge
of the clock. When low, the D1-D28 inputs will be latched and
redriven on every rising edge of the clock.
Data Input. Clocked in on the crossing of the rising edge of CLK
and the falling edge of CLK.
Chip select inputs – These pins initiate DRAM address/command
decodes, and as such at least one will be low when a valid
address/command is present. The Register can be programmed to
redrive all D inputs (CSGEN high) only when at least one chip select
input is low. If CSGEN, DCS0, and DCS1 inputs are high, D1-D28
inputs will be disabled.
The outputs of this register bit will not be suspended by the DCS0
and DCS1 controls
The outputs of this register bit will not be suspended by the DCS0
and DCS1 controls
Parity Input arrives one cycle after corresponding data input
Data Outputs that are suspended by the DCS0 and DCS1 controls
Data Output that will not be suspended by the DCS0 and DCS1
controls
Data Output that will not be suspended by the DCS0 and DCS1
controls
Data Output that will not be suspended by the DCS0 and DCS1
controls
Output Error bit, generated one cycle after the corresponding data
output
No Connection
11
Description
COMMERCIAL TEMPERATURE GRADE
IDT74SSTUBF32868A
7068/10