74SSTUBF32868ABKG IDT, Integrated Device Technology Inc, 74SSTUBF32868ABKG Datasheet - Page 15

• Manufacturer Part Number: 74SSTUBF32868ABKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 74SSTUBF32868ABKG

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 28
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -6mA
• Low Level Output Current: 6mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Invert/Non-Invert
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 176
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Register Timing
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
IDT74SSTUBF32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Qn, QODTn,
Dn, DODTn,
CSGEN
RESET
DCKEn
QCKEn
PARIN
NOTES:
1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held LOW for a
minimum time of t
2.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and
it will be valid on the n+3 clock pulse.
QERR
DCS0
DCS1
CLK
CLK
ACTMAX
t
ACT
, to avoid false error.
H, L, or X
n
t
SU
t
PDM,
CLK to Q
t
PDMSS
Data to QERR Latency
n +1
15
t
SU
CLK to QERR
t
H
t
PHL
n + 2
t
H
COMMERCIAL TEMPERATURE GRADE
n + 3
H or L
CLK to QERR
IDT74SSTUBF32868A
t
PHL,
t
PLH
n + 4
7068/10