74SSTUBF32868ABKG IDT, Integrated Device Technology Inc, 74SSTUBF32868ABKG Datasheet - Page 9

• Manufacturer Part Number: 74SSTUBF32868ABKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 74SSTUBF32868ABKG

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 28
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -6mA
• Low Level Output Current: 6mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Invert/Non-Invert
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 176
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Parity and Standby Function Table
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
IDT74SSTUBF32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
RESET
1
2
3
QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
4
error occurs on the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays
latched LOW for the LPM plus two clock cycles or until RESET is driven LOW.
H
H
H
H
H
H
H
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
PAR_IN arrives one clock cycle after the data to which it applies.
This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If
If DCS0, DCS1, and CSGEN are driven HIGH, the device is placed in low-power mode (LPM). If a parity
Floating
DCS0
X or
H
X
X
X
X
X
L
L
L
L
Floating
DCS1
X or
H
X
X
X
X
X
L
L
L
L
Floating
CLK
X or
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Floating
CLK
Inputs
X or
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
1
Σ of Inputs = H (D1 - D28)
9
X or Floating
Even
Even
Even
Even
Odd
Odd
Odd
Odd
X
X
COMMERCIAL TEMPERATURE GRADE
X or Floating
IDT74SSTUBF32868A
PAR_IN
H
H
H
H
X
X
L
L
L
L
2
Outputs
QERR
QERR
QERR
H
H
H
H
H
L
L
L
L
7068/10
0
0
3
4