APM86290 Applied Micro Circuits Corporation, APM86290 Datasheet

APM86290

Manufacturer Part Number

APM86290

Description

Manufacturer

Applied Micro Circuits Corporation

Datasheet

1.APM86290.pdf (2 pages)

Specifications of APM86290

Operating Temperature (min)

-40C

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Lead Free Status / RoHS Status

Supplier Unconfirmed

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Features

•

Offload Features

•

Queue Manager / Traffic Manager

•

High-Speed Interfaces

•

Other Interfaces

•

Dual-Core Power™465 processors

each with a Floating Point Unit

32 KB I- and 32 KB D-cache L1

256 KB L2 cache per processor

Hardware cache coherency

DDR3 memory controller with

optional ECC (72-bit)

Security acceleration (optional) for

IPSec, SSL, Kasumi, and public-

key protocols

Ethernet Classification Engine

Packet DMA

SLIMpro acceleration / offload

engine

Message passing architecture

Manages 256 fixed size Queues

Two GE ports (RGMII) with

Classification and TCP/IP off-load

One PCI Express® Gen 1/2 (x4/x1)

port

Two PCI Express® Gen 1/2 (x1)

ports

Two USB 2.0 Hosts with integrated

PHYs

One USB 2.0 OTG with integrated

PHY

Two SATA 2.0 ports

Local Bus (EBUS)

NAND Flash Controller

LCD Controller

Two I

Four UARTs

GPIOs

Two SPI

Two SDIO 3.0

JTAG / Trace

APM86290

The

generation of flexible processing nodes required to satisfy the demands of

intelligent all-IP networks and pervasive computing applications such as

Printing and Imaging. The APM86290 architecture provides a platform whose

components can play the role of various functions that operate today as

single/multiple CPUs, ASICs, and/or FPGAs, for performance and power

sensitive applications.

The Dual-Core IP Processor for Performance

Applications

The APM86290 architecture offers high-end

processing performance, in a low-power and

cost-optimized platform for complex processing

applications such as Printing and Imaging.

At the heart of the APM86290 are two 1.5-GHz

465 processor cores based on Power™

Architecture with full SMP support and

individual Floating Point processors. The Power

cores are programmable through an industry-

standard instruction set architecture (ISA). In

addition, these processors are assisted by a

rich set of configurable accelerators focused on

packet classification, security, packet/data

manipulation, and scheduling.

The APM86290 architecture introduces a

unique congestion-aware and management

capability to optimize its available processing

resources. This allows for full use control on

bandwidth and services.

Designed in 40nm bulk CMOS technology, the

APM86290 offers the best-in-class cost versus

processing performance in a low-power

envelope.

465 Processor Complex Features

The APM86290 incorporates two high

performance 465 processors. Each 465 has five

independent pipelines, a 32-KB data cache and

a 32-KB instruction cache (which are 64-way

set associative), and an IEEE floating point unit

(FPU). Each of the 465 cores has a dedicated

256KB L2 cache with hardware cache

coherency that attaches to the high-

performance Processor Local Bus 5 (PLB5).

APM86290 Key Features

AppliedMicro delivers the best-in-class feature

set for our Printing and Imaging customers.

Dedicated Ethernet Offload Engine

In order to meet the needs of very low power

and all-IP networks, the APM86290 includes a

dedicated Ethernet Offload Engine. The

Ethernet Offload Engine is capable of doing

Inline IPSec with greater than 2-Gbps line rate

throughput. It also provides for Inline TCP/IP

AppliedMicro APM86290

Dual-Core Power™ Processor

architecture provides the foundation for a new

and UDP checksums along with Energy

Efficiency Ethernet capabilities (802.3az).

Classification Engine

The classification engine provides for flow, CoS,

and port-based classification of data with a

greater than 2-Gbps line rate throughput. It is

programmable and can support IPv4, IPv6, and

AppleTalk, as well as customer proprietary

protocols.

Queue Manager / Traffic Manager (QMTM)

The Queue Manager / Traffic Manager is an

important design consideration for the

APM86290 and allows for the most efficient

moving of packets/data between the processors

and peripherals using a message passing

architecture. This is accomplished through a

central communication interface that offloads

software from the routing of packets and from

transaction synchronization.

The Queue Manager can be used to: centralize

management of all transaction traffic, reduce

communication overhead between software and

hardware, and perform inter-processor

message passing and work scheduling.

SLIMpro – Power Management

The APM86290 integrates a dedicated 32-bit

SLIMpro acceleration processor that provides

advanced capabilities such as dynamic power

management and higher layer network

acceleration. The SLIMpro processor leverages

the APM86290 message passing architecture

and other acceleration subsystems in order to

provide application-specific processor offloads.

It also provides advanced wake up capabilities

from Deep Sleep Mode such as Wake on LAN,

Wake on USB, Wake on PCIe, and Wake on

Interrupts.

Related parts for APM86290

APM86290 Summary of contents

Page 1

... Printing and Imaging. The APM86290 architecture provides a platform whose components can play the role of various functions that operate today as single/multiple CPUs, ASICs, and/or FPGAs, for performance and power sensitive applications ...

Page 2

... Copyright © 2010 Applied Micro Circuits Corporation. All Rights Reserved. APM86290_PB_v1.03_20101011vB 215 Moffett Park Drive, Sunnyvale, CA 94089 Advanced Security Engine The APM86290 can deliver advanced security capabilities with the optional security engine. This security engine utilizes the QMTM for the fastest possible throughput between the 465 processor, memory, and the security engine itself ...

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