LC5512MV-75F256C LATTICE SEMICONDUCTOR, LC5512MV-75F256C Datasheet - Page 12
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LC5512MV-75F256C
Manufacturer Part Number
LC5512MV-75F256C
Description
CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 150MHz EECMOS Technology 3.3V 256-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LC5512MV-75FN256C.pdf
(99 pages)
Specifications of LC5512MV-75F256C
Package
256FBGA
Family Name
ispXPLDÂ 5000MV
Device System Gates
150000
Number Of Macro Cells
512
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
193
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
150 MHz
Number Of Product Terms Per Macro
160
Ram Bits
262144
Memory Type
EEPROM/SRAM
Operating Temperature
0 to 90 °C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LC5512MV-75F256C
Manufacturer:
LATTICE
Quantity:
190
Company:
Part Number:
LC5512MV-75F256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LC5512MV-75F256C
Manufacturer:
LATTICE/莱迪斯
Quantity:
20 000
Lattice Semiconductor
Macrocell
The 32 registered macrocells in the MFB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a programmable register/latch flip-flop and the necessary clocks
and control logic to allow combinatorial or registered operation. All macrocells have an output that feeds the GRP.
Selected macrocells have an additional output that feeds the OSA and hence I/Os. This dual or concurrent output
capability from the macrocell gives efficient use of the hardware resources. One output can be a registered function
for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O
cell facilitates efficient use of the macrocell to construct high-speed input registers. Macrocell registers can be
clocked from one of several global or product term clocks available on the device. A global and product term clock
enable is also provided, eliminating the need to gate the clock to the macrocell registers directly. Reset and preset
for the macrocell register is provided from both global and product term signals. The macrocell register can be pro-
grammed to operate as a D-type register or a D-type latch. Figure 8 is a graphical representation of the macrocell.
Figure 8. Macrocell
Memory Modes
The ispXPLD 5000MX architecture allows the MFB to be configured as a variety of memory blocks as detailed in
Table 4. The remainder of this section details operation of each of the memory modes. Additional information
regarding the memory modes can also be found in TN1030,
Shared PT Reset
PTSA Bypass
Shared PT Clock
From PTSA
Global Reset
PT Preset
PT Reset
PT Clock
CLK0
CLK1
CLK2
CLK3
Shared
PT CE
D
Clk En
Clk
P
8
R/L
R
Q
Using Memory in ispXPLD 5000MX
ispXPLD 5000MX Family Data Sheet
From
I/O Cell
Output to
I/O Block
GRP
Devices.