LC5512MV-75F256C LATTICE SEMICONDUCTOR, LC5512MV-75F256C Datasheet - Page 48

• Manufacturer Part Number: LC5512MV-75F256C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 150MHz EECMOS Technology 3.3V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LC5512MV-75F256C

• Package: 256FBGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 193
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 150 MHz
• Number Of Product Terms Per Macro: 160
• Ram Bits: 262144
• Memory Type: EEPROM/SRAM
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
ispXP sysCONFIG Port Timing Specifications
sysCONFIG Write Cycle Timing
t
t
t
t
t
t
t
t
t
t
f
sysCONFIG Read Cycle Timing
t
t
t
t
f
t
SUCS
HCS
SUWD
HWD
PRGM
DINIT
IODISS
IOENSS
WH
WL
MAXW
HREAD
SUREAD
RH
RL
MAXR
CORD
Symbol
Input setup time of CS to CCLK rise
Hold time of CS to CCLK rise
Input setup time of write data to CCLK rise
Hold time of write data to CCLK rise
Low time to reset device SRAM
INIT delay time
User I/O disable
User I/O enable
Write clock High pulse width
Write clock Low pulse width
Write f
Hold time of READ to CCLK rise
Input setup time of READ High to CCLK rise
READ clock high pulse width
READ clock low pulse width
Read f
Clock to out for read data
MAX
MAX
Timing Parameter
44
ispXPLD 5000MX Family Data Sheet
Min.
10
10
18
18
15
18
18
—
—
—
—
—
—
1
0
5
1
Max.
50
27
27
25
—
—
—
—
—
—
—
—
—
—
—
—
5
Units
MHz
MHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns