LC5512MV-75F256C LATTICE SEMICONDUCTOR, LC5512MV-75F256C Datasheet - Page 52

• Manufacturer Part Number: LC5512MV-75F256C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 150MHz EECMOS Technology 3.3V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LC5512MV-75F256C

• Package: 256FBGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 193
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 150 MHz
• Number Of Product Terms Per Macro: 160
• Ram Bits: 262144
• Memory Type: EEPROM/SRAM
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
Switching Test Conditions
Figure 21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 14.
Figure 21. Output Test Load, LVTTL and LVCMOS Standards
Table 14. Test Fixture Required Components
Default LVCMOS 1.8 I/O (L -> H, H -> L)
LVCMOS I/O (L -> H, H -> L)
Default LVCMOS 1.8 I/O (Z -> H)
Default LVCMOS 1.8 I/O (Z -> L)
Default LVCMOS 1.8 I/O (H -> Z)
Default LVCMOS 1.8 I/O (L -> Z)
Note: Output test conditions for all other interfaces are determined by the respective standards.
Test Condition
106
106
106
R
—
—
—
1
106
106
106
R
—
—
—
2
35pF
35pF
35pF
48
35pF
5pF
5pF
C
L
LVCMOS2.5 = V
LVCMOS1.8 = V
LVCMOS3.3 = 1.5V
ispXPLD 5000MX Family Data Sheet
Timing Ref.
V
V
OL
OH
V
V
V
CCO
CCO
CCO
+ 0.15
- 0.15
/2
/2
/2
CCO
CCO
/2
/2
LVCMOS1.8 = 1.65V
LVCMOS3.3 = 3.0V
LVCMOS2.5 = 2.3V
1.65V
1.65V
1.65V
1.65V
V
1.8V
CCO