LC5512MV-75F256C LATTICE SEMICONDUCTOR, LC5512MV-75F256C Datasheet - Page 20

• Manufacturer Part Number: LC5512MV-75F256C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 150MHz EECMOS Technology 3.3V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LC5512MV-75F256C

• Package: 256FBGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 193
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 150 MHz
• Number Of Product Terms Per Macro: 160
• Ram Bits: 262144
• Memory Type: EEPROM/SRAM
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
Figure 15. PLL Block Diagram
Figure 16. Connection of Optional PLL Inputs and Outputs
In order to facilitate the multiply and divide capabilities of the PLL, each PLL has dividers associated with it: M, N
and K. The M divider is used to divide the clock signal, while the N divider is used to multiply the clock signal. The
K divider is only used when a secondary clock output is needed. This divider divides the primary clock output and
feeds to a separate global clock net. The V divider is used to provide lower frequency output clocks, while maintain-
ing a stable, high frequency output from the PLL’s VCO circuit. The PLL also has a delay feature that allows the out-
put clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. For more
information on the PLL, please refer to TN1003,
and ispMACH 5000VG
PLL_FBK
PLL_RST
CLK_IN
From Macrocell
From Macrocell
From Macrocell
*See pinout table for details
PLL_LOCK
Input Clock
CLK_OUT
(M) Divider
PLL_FBK
PLL_RST
To GRP
To GRP
To GRP
To GRP
Devices.
Programable
(N) Divider
Feedback
Delay
Loop
sysCLOCK PLL Usage Guide for ispXPGA, ispGDX2, ispXPLD
Detector
Phase
VCO
and
16
Post-scalar
ispXPLD 5000MX Family Data Sheet
Secondary
(V) Divider
(K) Divider
Clock
CLK_OUT
PLL_LOCK
SEC_OUT
I/O Pin*
I/O Pin*
I/O Pin*
Clock Net
Clock Net