LC5512MV-75F256C LATTICE SEMICONDUCTOR, LC5512MV-75F256C Datasheet - Page 57

• Manufacturer Part Number: LC5512MV-75F256C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 150MHz EECMOS Technology 3.3V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LC5512MV-75F256C

• Package: 256FBGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 193
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 150 MHz
• Number Of Product Terms Per Macro: 160
• Ram Bits: 262144
• Memory Type: EEPROM/SRAM
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
ispXPLD 5256MX Logic Signal Connections (Continued)
sysIO Bank LVDS Pair
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
-
-
-
-
-
-
-
-
-
-
-
10P
10N
11P
11N
12P
12N
13P
13N
14P
14N
15P
15N
16P
16N
17P
17N
18P
18N
19P
19N
4N
5N
6N
7N
8N
9N
5P
6P
7P
8P
9P
-
-
-
-
-
-
-
-
-
-
-
-
Primary Macrocell/
GND (Bank 1)
GND (Bank 1)
GND (Bank 2)
PROGRAMB
B16/VREF1
A18/READ
A20/CCLK
Function
A16/CSB
VCCO1
VCCO1
VCCO2
DONE
CFG0
VCC
VCC
A22
A24
A26
A28
B10
B12
B14
B18
B20
B21
B22
B24
B26
B28
B30
C10
C12
C0
C2
C4
C5
C6
C8
B2
B4
B5
B6
B8
Macrocell 1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
C0
C1
C2
C3
C4
C5
C6
C7
A9
53
Alternate Outputs
-
-
-
-
-
-
-
-
-
-
-
-
Macrocell 2
ispXPLD 5000MX Family Data Sheet
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
D0
D1
D2
D3
D4
D5
D6
D7
B9
-
-
-
-
-
-
-
-
-
-
-
-
Alternate Input
C11
C13
A17
A19
A21
A23
A25
A27
A29
B11
B13
B15
B17
B19
B23
B25
B27
B29
B31
B3
B7
B9
C1
C3
C7
C9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND (Bank 1)
GND (Bank 1)
GND (Bank 2)
Ball Number
256 fpBGA
VCCO1
VCCO2
VCC01
VCC
VCC
N10
R11
M10
M11
T10
T11
T12
P10
R10
T13
M2
M4
M6
M8
M9
N1
N3
P4
N5
R3
R7
N7
P7
R8
P8
N8
R9
P9
N9
L5
L8
T7
T8
L9
T9