IP4051CX11/LF,135 NXP Semiconductors, IP4051CX11/LF,135 Datasheet - Page 11

• Manufacturer Part Number: IP4051CX11/LF,135
• Description: IC EMI FILTER MMC ESD PROT 11CSP
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of IP4051CX11/LF,135

• Capacitance: 25pF
• Package / Case: 11-CSP
• Resistance (ohms): 47, 13K, 56K
• Resistance In Ohms: 47, 13K, 56K
• Channels: 4 Channels
• Termination Style: SMD/SMT
• Tolerance: -
• Power (watts): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Tolerance: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: /T3 934057926135 IP4051CX11/LF

NXP Semiconductors
AN10911_1
Application note
3.2 Bus timing conditions
3.3 Capacitive load at the interface conditioning device output
The MMC interface has different timing requirements for its default mode and the
high-speed mode running up to 52 MHz. Special attention should be paid to the clock
signal rise time/fall time requirement (3 ns maximum) which is similar to the high-voltage
range cards and the SD-memory card timing conditions (see
Also, a reduced clock speed of up to 26 MHz can be used with these cards to save power
in appliances that do not require high data rates.
As all NXP devices support the high-speed mode that supersedes the default-mode
requirements, only these requirements are taken into account here. However, the devices
explained in this document support both, the default-mode and the high-speed mode.
Table 7.
[1]
[2]
Please refer to
The drawings depicted in
specification-compliant bus system that includes high-level ESD protection and EMI
filtering. Nevertheless, most implementations used are basically related to the
SD-memory card application and use only slightly higher total channel capacitances,
reaching the SD specification for the value of C
Symbol
f
t
t
PP
rise
fall
Other timing parameters such as hold time, set-up time, high-time and low-time are dependent on the
host / MMC interface and are not significantly influenced by the NXP interface conditioning devices.
Please refer to
MMC timing conditions (high-speed mode)
Parameter
operating clock frequency
high-speed mode clock rise time
high-speed mode clock fall time
Section 2.3
All information provided in this document is subject to legal disclaimers.
Ref.
2, chapter 12.7.1 for further details.
Rev. 01 — 29 April 2010
Figure 3
for a detailed overview and calculation.
SD(HC)-memory card and MMC interface conditioning
show that it is difficult to build an MMC
HOST
[1]
+ C
BUS
[2]
.
Table
Min
0
-
-
3).
AN10911
© NXP B.V. 2010. All rights reserved.
Max
(26)/52
3
3
Unit
MHz
ns
ns
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