ICS94201DFLFT IDT, Integrated Device Technology Inc, ICS94201DFLFT Datasheet
ICS94201DFLFT
Specifications of ICS94201DFLFT
Related parts for ICS94201DFLFT
ICS94201DFLFT Summary of contents
Page 1
Integrated Circuit Systems, Inc. Programmable System Frequency Generator for PII/III™ Recommended Application: 810/810E and Solano (815) type chipset Output Features: • CPUs @ 2.5V • SDRAM @ 3.3V • 3V66 @ 3.3V • 8 ...
Page 2
ICS94201 General Description The ICS94201 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all necessary clock signals for such a system. The ICS94201 belongs to ICS new generation of programmable ...
Page 3
General I C serial interface information for the ICS94201 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command ...
Page 4
ICS94201 Brief I Programmable System Frequency Generator Register Name Func tionality & Frequenc y Select Register Output Control Registers Byte Count Read Back Register Latc hed Inputs Read Back Register W atchdog Control Regis ters VCO Control S election B ...
Page 5
Byte 0: Functionality and frequency select register (Default= ...
Page 6
ICS94201 Byte 1: Output Control Register (1 = enable disable ...
Page 7
Byte 7: Latch Inputs Readback Register ...
Page 8
ICS94201 Byte 13: ICS Reserved Register ...
Page 9
Note: 1. User needs to ensure step 3 & carried out. Systems with the wrong spread percentage and/or group to group divider ratio programmed into bytes 16-20 could be unstable. Step 3 & 7 assure the correct spread ...
Page 10
ICS94201 Byte 20: Output Dividers Control Register ...
Page 11
Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . ...
Page 12
ICS94201 Electrical Characteristics - CPU 70º 2.5 V +/-5 DDL PARAMETER SYMBOL 1 Output Impedance R DSP2B 1 Output Impedance R DSN2B Output High Voltage V OH2B Output Low Voltage V ...
Page 13
Electrical Characteristics - IOAPIC 70º 2.5 V +/-5 DDL PARAMETER SYMBOL 1 Output Impedance R DSP4B 1 Output Impedance R DSN4B Output High Voltage V OH4B Output Low Voltage V OL4B ...
Page 14
ICS94201 Electrical Characteristics - PCI 70º 3.3 V +/-5 PARAMETER SYMBOL 1 Output Impedance R DSP1 1 Output Impedance R DSN1 Output High Voltage V OH1 Output Low Voltage V ...
Page 15
Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS94201 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these ...
Page 16
ICS94201 Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown ...
Page 17
CPU 66MHz CPU 100MHz CPU 133MHz SDRAM 100MHz SDRAM 133MHz 3.5V 66MHz PCI 33MHz APIC 33MHz REF 14.318MHz USB 48MHz 0428B - 11/28/05 10ns 20ns Cycle Repeats Group Offset Waveforms 17 ICS94201 30ns 40ns ...
Page 18
ICS94201 INDEX INDEX AREA AREA 45° 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C 300 mil SSOP Package Ordering Information ...
Page 19
Revision History Rev. Issue Date Description B 11/28/2005 Added LF Ordering Information 0428B - 11/28/05 19 ICS94201 Page # 18 ...