ICS94201DFLFT IDT, Integrated Device Technology Inc, ICS94201DFLFT Datasheet - Page 10

• Manufacturer Part Number: ICS94201DFLFT
• Description: IC FREQ GENERATOR PROGR 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS94201DFLFT

• Input: Crystal
• Output: Clock
• Frequency - Max: 500MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 94201DFLFT

ICS94201
Note: Changing bits in these registers results in
Byte 22: Group Skew Control Register
Note: Default 3V66 to PCI skew is 2.5ns bit [7:4]=1001.
Byte 24: Output Rise/Fall Time Select Register
Byte 20: Output Dividers Control Register
0428B - 11/28/05
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
frequency divider ratio changes. Incorrect
configuration of group gear ratio can cause
system malfunction.
Each increment or decrement of bit 4 to 7 will
introduce 100ps delay or advance on all PCI
clocks.
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
P
P
P
W
W
W
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
D
D
D
O
O
O
O
O
O
O
O
3
3
3
3
R (
R (
R (
R (
R (
R
2
R (
P
3
S
R (
V
V
V
V
V
, 4
D
I C
u
u
u
u
u
u
u
u
E
s e
s e
s e
s e
s e
s e
s e
6 6
6 6
6 6
6 6
6 6
p t
p t
p t
p t
p t
p t
p t
p t
8 4
R
F
r e
r e
r e
r e
r e
r e
r e
0
A
t u
t u
t u
t u
t u
t u
t u
t u
0
M
=
o t
o t
o t
o t
0
e v
e v
e v
e v
e v
e v
e v
=
M
N
=
D
D
D
D
D
D
D
D
z h
N
) d
) d
) d
) d
) d
) d
) d
N
P
P
P
P
r o
v i
v i
v i
v i
v i
v i
v i
v i
0
r o
I C
I C
I C
I C
r o
=
0
m
d i
d i
d i
d i
d i
d i
d i
d i
m
=
N
m
D
D
D
l a
r e
r e
r e
r e
r e
r e
r e
r e
S
S
S
S
N
l a
r o
e
e
e
l a
e k
e k
e k
e k
1 ,
r o
1 ,
c s
c s
c s
M
M
M
M
M
M
M
M
m
1 ,
w
w
w
w
m
=
i r
i r
i r
l a
U
U
U
U
U
U
U
U
=
W
=
l a
W
t p
t p
i B
i B
i B
i B
t p
1 ,
X
X
X
X
X
X
X
X
W
1 ,
e
e
o i
o i
o i
3 t
2 t
1 t
0 t
k a
C
C
C
C
C
C
C
C
=
e
k a
=
k a
n
n
n
W
n o
n o
n o
n o
n o
n o
n o
n o
W
e
r t
r t
r t
r t
r t
r t
r t
r t
k a
e
l o
l o
l o
l o
l o
l o
l o
l o
k a
B
B
B
B
B
B
B
B
t i
t i
t i
t i
t i
t i
t i
t i
3 2
2 2
1 2
0 2
9 1
8 1
7 1
6 1
10
Notes:
1. PWD = Power on Default
2. The power on default for byte 16-20 depends on the hardware
3. If Byte 8 bit 7 is driven to "1" meaning programming is
Note: This is an unused register. Writing to this register will
Byte 23: Group Skew Control Register
Note: Default 3V66 to IOAPIC skew is 2.5ns bit [3:0]=0111.
Byte 21: ICS Reserved Register
(latch inputs FS[0:4]) or I
to read back and re-write the values of these 5 registers when
VCO frequency change is desired for the first pass.
intended, Byte 21-24 will lose their default power up value.
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
not affect device performance or functionality.
Each increment or decrement of bit 4 to 7 will introduce
100ps delay or advance on all IOAPIC clocks.
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
P
P
W
W
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
D
D
R (
R (
R (
R (
R (
R (
R (
R (
R (
R (
R (
R (
3
3
3
3
V
V
V
V
s e
s e
s e
s e
s e
s e
s e
s e
s e
s e
s e
s e
6 6
6 6
6 6
6 6
r e
r e
r e
r e
r e
r e
r e
r e
r e
r e
r e
r e
2
o t
o t
o t
o t
e v
e v
e v
e v
e v
e v
e v
e v
e v
e v
e v
e v
C (Byte 0 bit [1:7]) setting. Be sure
) d
) d
) d
) d
I
I
I
I
) d
) d
) d
) d
) d
) d
) d
) d
O
O
O
O
A
A
A
A
P
P
P
P
D
D
C I
C I
C I
C I
e
e
c s
c s
S
S
S
S
e k
e k
e k
e k
i r
i r
w
w
w
w
t p
t p
B
B
B
B
o i
o i
t i
t i
t i
t i
n
n
3
2
1
0