ICS307G-03LF IDT, Integrated Device Technology Inc, ICS307G-03LF Datasheet - Page 5

• Manufacturer Part Number: ICS307G-03LF
• Description: IC CLK SOURCE SRL PROGR 16-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of ICS307G-03LF

• Pll: Yes
• Input: Clock, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:3
• Differential - Input:output: No/No
• Frequency - Max: 270MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 270MHz
• Number Of Elements: 1
• Supply Current: 24mA
• Pll Input Freq (min): 100KHz
• Pll Input Freq (max): 300MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Output Frequency Range: 0.0002 to 270MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 307G-03LF; 800-1028; 800-1028-5; 800-1028

Table 5. Output Divider for Output 1
IDT® SERIALLY PROGRAMMABLE CLOCK SOURCE
Divide
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
Value
1029
1030
1032
2056
2058
2060
2064
4112
4116
4120
4128
8224
8232
10
11
12
13
14
15
36
37
38
39
2
3
4
5
6
7
8
9
109 108 107 106 105 104 103
(increments of 1)
(increments of 2)
(increments of 4)
(increments of 8)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
Bits
102
X
X
X
X
X
X
X
X
X
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
101 100 99 98 97 96 95 Rule
X
X
X
X
X
X
X
X
X
1
1
1
0
0
0
0
0
0
1
0
1
1
1
0
1
1
1
0
1
1
1
X
X
X
X
X
X
1
X
0
X
0
X
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
5
X
X
X
X
X
0
0
0
1
1
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
1
1
1
0
1
1
1
0
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
subtract 6 from the desired divide
value, convert to binary, invert, and
apply to bits 102..98
set bits [97..95] = 100
output divide =
((([109..101]+3)*2)+[98])*2^[100..99]
set bits [95..97] = 101
set bits [95..97] = 101
(
38-8232)
†
SER PROG CLOCK SYNTHESIZER
apply Rule from Divide Values 14-37
apply Rule from Divide Values 14-37
apply Rule from Divide Values 14-37
this Rule applies to Divide Values
ICS307-03
†
REV L 032911