MPC9350ACR2 IDT, Integrated Device Technology Inc, MPC9350ACR2 Datasheet - Page 3

• Manufacturer Part Number: MPC9350ACR2
• Description: IC PLL CLOCK DRIVER LV 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9350ACR2

• Pll: Yes with Bypass
• Input: LVCMOS, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:9
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9350
Low Voltage PLL Clock Driver
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 1. Pin Description
Table 2. Function Table
Table 3. Absolute Maximum Ratings
XTAL1, XTAL2
TCLK
FBSEL
REF_SEL
FSELA
FSELB
FSELC
FSELD
OE
QA
QB
QC0, QC1
QD0 – QD4
GND
V
V
V
V
V
I
I
T
IN
OUT
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
Symbol
CCA
CC
CC
IN
OUT
S
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
REF_SEL
Number
PLL_EN
Control
FBSEL
FSELA
FSELB
FSELC
FSELD
OE
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Supply
Supply
Supply
Default
0
1
0
0
0
0
0
0
Characteristics
Name
Selects XTAL
Test mode with PLL disabled. The input clock is
directly routed to the output dividers
Selects feedback divider ÷ 32
VCO = 32 * Input reference clock
Outputs enabled
QA = VCO ÷ 2
QB = VCO ÷ 4
QC = VCO ÷ 4
QD = VCO ÷ 4
(1)
Analog
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
V
V
CC
CC
Type
0
3
Crystal oscillator terminals
Single ended reference clock signal or test clock
Selects feedback divider ratio
Selects input reference source
Output A divider selection
Output B divider selection
Outputs C divider selection
Outputs D divider selection
Output enable/disable
Bank A clock output
Bank B clock output
Bank C clock outputs
Bank D clock outputs
Negative power supply
Positive power supply for the PLL
Positive power supply for I/O and core
–0.3
–0.3
–0.3
Min
–40
Selects TCLK
PLL enabled. The VCO output is routed to the
output dividers
Selects feedback divider ÷ 16
VCO = 16 * Input reference clock
Outputs disabled
QA = VCO ÷ 4
QB = VCO ÷ 8
QC = VCO ÷ 8
QD = VCO ÷ 8
V
V
Description
CC
CC
Max
±20
±50
125
4.6
+0.3
+0.3
1
Unit
mA
mA
°C
V
V
V
Condition
MPC9350
NETCOM
MPC9350
3