MPC9350ACR2 IDT, Integrated Device Technology Inc, MPC9350ACR2 Datasheet - Page 4

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MPC9350ACR2

Manufacturer Part Number
MPC9350ACR2
Description
IC PLL CLOCK DRIVER LV 32-LQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet

Specifications of MPC9350ACR2

Pll
Yes with Bypass
Input
LVCMOS, Crystal
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
2:9
Differential - Input:output
No/No
Frequency - Max
200MHz
Divider/multiplier
Yes/No
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
200MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC9350ACR2
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9350
Low Voltage PLL Clock Driver
Table 4. DC Characteristics (V
Table 5. AC Characteristics (V
MPC9350
4
V
V
V
V
I
Z
C
C
I
I
f
f
f
f
f
t
t
t
t
t
t
BW
t
t
t
t
IN
CCA
CC
V
ref
XTAL
VCO
MAX
refDC
r
sk(o)
PW
r
PLZ, HZ
PZL, LZ
JIT(CC)
JIT(PER)
LOCK
JIT(∅)
1. The MPC9350 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
1. AC characteristics apply for parallel output termination of 50Ω to V
, t
, t
OUT
IH
IL
OH
OL
Symbol
IN
PD
TT
Symbol
f
f
transmission line to a termination voltage of V
Input high voltage
Input low voltage
Output High Voltage
Output Low Voltage
Input Current
Output impedance
Input capacitance
Power Dissipation Capacitance
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output termination voltage
Input Frequency
Static Test Mode
Crystal Oscillator Frequency
VCO Frequency
Maximum Output Frequency
Reference Input Duty Cycle
TLCK Input Rise/Fall Time
Output-to-output Skew
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
PLL closed loop bandwidth
Cycle-to-cycle jitter
Period Jitter
Maximum PLL Lock Time
I/O Phase Jitter (RMS)
Characteristics
Characteristics
÷ 16 feedback (V
÷ 16 feedback (V
÷ 32 feedback (V
÷ 32 feedback (V
CC
CC
= 3.3 V ± 5%, T
= 3.3 V ± 5% or V
multiple frequencies
single frequency
÷ 16 feedback
÷ 32 feedback
÷ 16 feedback
÷ 32 feedback
V
V
CC
CC
CC
CC
TT
CC
CC
÷ 2 output
÷ 4 output
÷ 8 output
. Alternatively, the device drives up to two 50 Ω series terminated transmission lines.
= 3.3 V)
= 2.5 V)
= 3.3 V)
= 2.5 V)
= 2.5 V
= 3.3 V
A
= -40° to 85°C)
CC
= 2.5 V ± 5%, T
–0.3
Min
2.0
2.4
12.5
6.25
Min
200
100
0.1
10
50
25
25
45
TT
0
4
.
14 – 17
V
Typ
4.0
CC
10
A
= -40° to 85°C)
÷2
2.0 – 8.0
1.0 – 4.0
1.5 – 3.5
0.7 – 2.0
5 – 20
Typ
100
0.5
45
50
30
30
80
V
CC
Max
0.55
0.30
200
0.8
1.0
10
+ 0.3
(1)
Max
12.5
300
400
200
100
150
200
300
150
200
1.0
1.0
1.0
25
25
50
75
55
10
10
1
Advanced Clock Drivers Devices
Unit
mA
mA
µA
pF
pF
V
V
V
V
V
V
Freescale Semiconductor
LVCMOS
LVCMOS
I
I
I
V
Per Output
V
All V
OH
OL
OL
IN
CCA
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ns
ns
ps
ps
ns
ns
ns
ps
ps
ps
ps
ps
= 24 mA
= 12 mA
%
= –24 mA
= 0 V or V
CC
Pin
Pins
Condition
FBSEL = 1
FBSEL = 0
PLL_EN = 0
XTAL inputs
PLL_EN = 1
0.7 V to 1.7 V
0.8 V to 2.0 V
T=Clock period
see
RMS value
Condition
(1)
Figure 10
IN
= V
CC
NETCOM
MPC9350

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