MPC9350ACR2 IDT, Integrated Device Technology Inc, MPC9350ACR2 Datasheet - Page 9

• Manufacturer Part Number: MPC9350ACR2
• Description: IC PLL CLOCK DRIVER LV 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9350ACR2

• Pll: Yes with Bypass
• Input: LVCMOS, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:9
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9350
Low Voltage PLL Clock Driver
Advanced Clock Drivers Devices
Freescale Semiconductor
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs.
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device.
Figure 8. Output-to-Output Skew t
Figure 11. Cycle-to-Cycle Jitter
T
N
T
N+1
t
SK(O)
The time from the maximum low level voltage to minimum high
level of a clock signal, expressed in ns.
T
JIT(CC)
t
F
Figure 10. Transition Time Test Reference
= |T
SK(O)
N
–T
N+1
V
V
GND
V
V
GND
|
CC
CC
CC
CC
÷ 2
÷ 2
9
t
R
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles.
V
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
CC
0.55
=3.3 V
2.4
Figure 9. Output Duty Cycle (DC)
V
CC
T
0
1.8 V
0.6 V
Figure 12. Period Jitter
=2.5 V
t
P
T
0
DC = t
P
/T
T
JIT(PER)
0
x 100%
= |T
N
–1/f
V
V
GND
0
|
CC
CC
MPC9350
÷ 2
NETCOM
MPC9350
9