MPC9350ACR2 IDT, Integrated Device Technology Inc, MPC9350ACR2 Datasheet - Page 7

• Manufacturer Part Number: MPC9350ACR2
• Description: IC PLL CLOCK DRIVER LV 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9350ACR2

• Pll: Yes with Bypass
• Input: LVCMOS, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:9
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9350
Low Voltage PLL Clock Driver
Advanced Clock Drivers Devices
Freescale Semiconductor
Power Supply Filtering
such, it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC9350 provides separate
power supplies for the output buffers (V
phase-locked loop (V
the high switching noise digital outputs from the relatively
sensitive internal analog phase-locked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient; however, in a digital system
environment where it is more difficult to minimize noise on the
power supplies, a second level of isolation may be required.
The simplest form of isolation is a power supply filter on the
V
power supply filter scheme. The MPC9350 is most
susceptible to noise with spectral content in the 10 kHz to
5 MHz range; therefore, the filter should be designed to target
this range. The key parameter that needs to be met in the
final filter design is the DC voltage drop that will be seen
between the V
From the data sheet the I
through the V
assuming that a minimum of 3.0 V must be maintained on the
V
3.3 V V
must have a resistance of 10–15 Ω to meet the voltage drop
criteria for V
be selected to maintain the minimum V
2.375 V for the PLL supply pin for proper operation. The RC
filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral
content is above 20 kHz. As the noise frequency crosses the
series resonant point of an individual capacitor, its overall
impedance begins to look inductive and, thus, increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the bandwidth of the PLL. It is
recommended that the user start with an 8–10 Ω resistor to
avoid potential V
higher value resistors when a higher level of attenuation is
shown to be needed.
CCA
CCA
The MPC9350 is a mixed analog/digital product and as
The purpose of this design technique is to try and isolate
pin. Very little DC voltage drop can be tolerated when a
pin for the MPC9350.
CC
supply is used. The resistor shown in
CC
CCA
MPC9350
CC
Figure 3. Power Supply Filter
= 3.3 V. For V
CC
supply and the V
pin) is typically 10 mA (15 mA maximum),
V
drop problems and only move to the
V
CCA
CC
CCA
) of the device.
VCCA
0.01µF
Figure 3
CC
current (the current sourced
= 2.5 V operation, R
R
S
=5–15Ω
CCA
22µF
illustrates a typical
2.5V or 3.3V
pin of the MPC9350.
CC
CCO
0.01µF
specification of
) and the
Figure 3
S
must
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minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems in
most designs.
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 15 Ω, the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 Ω resistance to V
thus, only a single terminated line can be driven by each
output of the MPC9350 clock driver. For the series terminated
case, however, there is no DC current draw, thus the outputs
can drive multiple series terminated lines.
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9350 clock driver is effectively doubled
due to its capability to drive multiple lines.
results of an output driving a single line versus two lines. In
both cases, the drive capability of the MPC9350 output buffer
is more than sufficient to drive 50 Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
IN
IN
Although the MPC9350 has several design features to
The MPC9350 clock driver was designed to drive high-
This technique draws a fairly high level of DC current, and
The waveform plots in
Figure 4. Single versus Dual Transmission Lines
MPC9350
MPC9350
Output
Output
Buffer
Buffer
14Ω
14Ω
CC
÷2.
R
R
R
S
S
S
Figure 5
= 36Ω
= 36Ω
= 36Ω
show the simulation
Z
Z
Z
O
O
O
= 50Ω
= 50Ω
= 50Ω
Figure 4
illustrates
MPC9350
OutA
OutB0
OutB1
NETCOM
MPC9350
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