IDT82V3255TFG8 IDT, Integrated Device Technology Inc, IDT82V3255TFG8 Datasheet - Page 26

• Manufacturer Part Number: IDT82V3255TFG8
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG8

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG8

3.8
selection, it can be switched by setting the related registers (refer to
Chapter 3.6.1 External Fast Selection (T0 only)
Selection) any time. In this case, whether the input clock is qualified for
DPLL locking does not affect the clock switch. If the T4 selected input
clock is a T0 DPLL output, it can only be switched by setting the
T0_FOR_T4 bit.
clock switch depends on its validity and priority. If the current selected
input clock is disqualified, a new qualified input clock may be switched
to.
3.8.1
clock quality monitoring (refer to
toring). When all of the following conditions are satisfied, the input clock
is valid; otherwise, it is invalid.
from that of the T4 selected input clock. The validity qualification of the
T4 selected input clock is the same as the above. The T0 selected input
clock is valid when all of the above and the following conditions are sat-
isfied; otherwise, it is invalid.
bit (n = 1, 2 or 3) / INn_DIFF
ity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), the
INn_CMOS
3
selected input clock changes from ‘valid’ to ‘invalid’, the
T0_MAIN_REF_FAILED
bit is ‘1’, an interrupt will be generated. This interrupt can also be indi-
cated by hardware - the TDO pin, as determined by the
LOS_FLAG_TO_TDO bit. When the TDO pin is used to indicate this
interrupt, it will be set high when this interrupt is generated and will
remain high until this interrupt is cleared.
Functional Description
IDT82V3255
bit is ‘1’, an interrupt will be generated.
If the input clock is selected by External Fast selection or by Forced
When the input clock is selected by Automatic selection, the input
For all the input clocks, the validity depends on the results of input
The validity qualification of the T0 selected input clock is different
The validities of all the input clocks are indicated by the INn_CMOS
When the T0 selected input clock has failed, i.e., the validity of the T0
• No no-activity alarm (the INn_CMOS_NO_ACTIVITY_ALARM /
• No frequency hard alarm (the INn_CMOS_FREQ_HARD_
• If the IN_NOISE_WINDOW bit is ‘1’, all the edges of the input
• No phase lock alarm, i.e., the INn_CMOS_PH_LOCK_ALARM /
• If the ULTR_FAST_SW bit is ‘1’, the T0 selected input clock
INn_DIFF_NO_ACTIVITY_ALARM bit is ‘0’);
ALARM / INn_DIFF_FREQ_HARD_ALARM bit is ‘0’);
clock of 2 kHz, 4 kHz or 8 kHz drift inside ±5%; if the
IN_NOISE_WINDOW bit is ‘0’, this condition is ignored.
INn_DIFF_PH_LOCK_ALARM bit is ‘0’;
misses less than (<) 2 consecutive clock cycles; if the
ULTR_FAST_SW bit is ‘0’, this condition is ignored.
SELECTED INPUT CLOCK SWITCH
INPUT CLOCK VALIDITY
2
/ INn_DIFF
1
2
bit will be set. If the T0_MAIN_REF_FAILED
bit will be set. If the INn_CMOS
1
bit (n = 1 or 2). When the input clock valid-
Chapter 3.5 Input Clock Quality Moni-
&
Chapter 3.6.2 Forced
3
/ INn_DIFF
1
2
26
3.8.2
input clock switch is different from T4 input clock switch.
as selected by the REVERTIVE_MODE bit.
that whether the selected input clock is switched when another qualified
input clock with a higher priority than the current selected input clock is
available for selection. In Non-Revertive switch, input clock switch is
minimized.
different from that for T4 selection, as shown in
Table 14: Conditions of Qualified Input Clocks Available for T0 & T4
Selection
satisfied.
3.8.2.1
another qualified input clock with a higher priority than the current
selected input clock is available.
fied:
switch. If more than one qualified input clock is available and has the
same priority, the input clock with the smallest ‘n’ is selected. See
Table 9
T0
T4
When the device is configured as Automatic input clock selection, T0
For T0 path, Revertive and Non-Revertive switches are supported,
For T4 path, only Revertive switch is supported.
The difference between Revertive and Non-Revertive switches is
Conditions of the qualified input clocks available for T0 selection are
The input clock is disqualified if any of the above conditions is not
In summary, the selected input clock can be switched by:
In Revertive switch, the selected input clock is switched when
The selected input clock is switched if any of the following is satis-
A qualified input clock with the highest priority is selected by revertive
• Valid, i.e., the INn_CMOS
• Priority
• Valid (all the validity conditions listed in
• Priority
• External Fast selection (supported by T0 path only);
• Forced selection;
• Revertive switch;
• Non-Revertive switch (supported by T0 path only);
• T4 DPLL locked to T0 DPLL output (supported by T4 path only).
• the selected input clock is disqualified;
• another qualified input clock with a higher priority than the
Conditions of Qualified Input Clocks Available for T0 & T4 Selection
_PRIORITY[3:0] / INn_DIFF_SEL_PRIORITY[3:0] bits are not ‘0000’
ity
_PRIORITY[3:0] / INn_DIFF_SEL_PRIORITY[3:0] bits are not ‘0000’
selected input clock is available.
for the ‘n’ assigned to each input clock.
are satisfied);
SELECTED INPUT CLOCK SWITCH
Revertive Switch
enabled,
enabled,
i.e.,
i.e.,
1
/ INn_DIFF
the
the
corresponding
corresponding
1
Chapter 3.8.1 Input Clock Valid-
bit is ‘1’;
Table
December 3, 2008
14:
INn_CMOS_SEL
INn_CMOS_SEL
WAN PLL