IDT82V3255TFG8 IDT, Integrated Device Technology Inc, IDT82V3255TFG8 Datasheet - Page 4

• Manufacturer Part Number: IDT82V3255TFG8
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG8

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG8

Table of Contents
4 MICROPROCESSOR INTERFACE .................................................................................................................................. 43
5 JTAG ................................................................................................................................................................................ 45
6 PROGRAMMING INFORMATION .................................................................................................................................... 46
7 THERMAL MANAGEMENT ........................................................................................................................................... 111
8 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 112
IDT82V3255
3.11 T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 34
3.12 T0 / T4 APLL ................................................................................................................................................................................................. 36
3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 36
3.14 INTERRUPT SUMMARY ............................................................................................................................................................................... 40
3.15 T0 AND T4 SUMMARY ................................................................................................................................................................................. 40
3.16 POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 41
3.17 LINE CARD APPLICATION .......................................................................................................................................................................... 42
6.1 REGISTER MAP ............................................................................................................................................................................................ 46
6.2 REGISTER DESCRIPTION ........................................................................................................................................................................... 51
7.1 JUNCTION TEMPERATURE ...................................................................................................................................................................... 111
7.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 111
7.3 HEATSINK EVALUATION .......................................................................................................................................................................... 111
8.1 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 112
8.2 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 112
8.3 I/O SPECIFICATIONS ................................................................................................................................................................................. 113
3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 32
3.11.1 PFD Output Limit ............................................................................................................................................................................ 34
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 34
3.11.3 PBO (T0 only) ................................................................................................................................................................................. 34
3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 34
3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 34
3.13.1 Output Clocks ................................................................................................................................................................................. 36
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 38
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10 Synchronization Configuration Registers ................................................................................................................................. 109
8.3.1
8.3.2
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 31
3.10.1.5 Holdover Mode ................................................................................................................................................................. 31
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 32
3.10.2.1 Free-Run Mode ................................................................................................................................................................ 32
3.10.2.2 Locked Mode .................................................................................................................................................................... 32
3.10.2.3 Holdover Mode ................................................................................................................................................................. 32
3.11.5.1 T0 Path ............................................................................................................................................................................. 34
3.11.5.2 T4 Path ............................................................................................................................................................................. 35
Global Control Registers ............................................................................................................................................................... 51
Interrupt Registers ......................................................................................................................................................................... 58
Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 62
Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 73
T0 / T4 DPLL Input Clock Selection Registers ............................................................................................................................. 84
T0 / T4 DPLL State Machine Control Registers ........................................................................................................................... 88
T0 / T4 DPLL & APLL Configuration Registers ............................................................................................................................ 90
Output Configuration Registers .................................................................................................................................................. 103
PBO & Phase Offset Control Registers ...................................................................................................................................... 107
CMOS Input / Output Port ............................................................................................................................................................ 113
PECL / LVDS Input / Output Port ................................................................................................................................................ 114
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 32
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 32
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 32
3.10.1.5.4 Manual ........................................................................................................................................................... 32
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 32
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December 3, 2008
WAN PLL