IDT82V3255TFG8 IDT, Integrated Device Technology Inc, IDT82V3255TFG8 Datasheet - Page 44

• Manufacturer Part Number: IDT82V3255TFG8
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG8

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG8

Table 31: Read Timing Characteristics in Serial Mode
Table 32: Write Timing Characteristics in Serial Mode
Microprocessor Interface
IDT82V3255
Symbol
Symbol
t
t
t
t
t
t
t
pw1
pw2
t
t
t
t
t
t
t
t
su1
su2
t
out
pw1
pw2
t
t
T
d1
d2
h1
h2
su1
su2
t
TI
t
out
in
T
h1
h2
in
TI
SCLK
CS
SDO
SDI
Time between consecutive Read-Read or Read-Write accesses
Time between consecutive Write-Write or Write-Read accesses
CS rising edge to SDO high impedance delay time
Valid CS after valid SCLK hold time (CLKE = 0/1)
t
su2
t
su1
R/W
Valid SDI after valid SCLK hold time
Valid SDI after valid SCLK hold time
Valid CS after valid SCLK hold time
Valid SCLK to valid data delay time
(CS rising edge to CS falling edge)
Valid SDI to valid SCLK setup time
(CS rising edge to CS falling edge)
One cycle time of the master clock
Valid SDI to valid SCLK setup time
One cycle time of the master clock
Valid CS to valid SCLK setup time
Valid CS to valid SCLK setup time
t
h1
SCLK pulse width high
SCLK pulse width high
A0
SCLK pulse width low
SCLK pulse width low
Delay of output pad
Delay of output pad
Delay of input pad
Delay of input pad
Parameter
Parameter
A1
Figure 16. Serial Write Timing Diagram
A2
t
pw1
A3
t
pw2
A4
A5
44
A6
High-Z
D0
3.5T + 5
3.5T + 5
D1
3.5T
3.5T
Min
14
10
Min
4
6
5
14
10
4
6
5
D2
D3
12.86
D4
12.86
Typ
Typ
10
10
5
5
5
5
D5
D6
D7
Max
Max
t
h2
December 3, 2008
WAN PLL
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns