IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 109

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

IN_FREQ_READ_STS - Input Clock Frequency Read Value
IN1_IN2_STS - Input Clock 1 & 2 Status
Programming Information
IDT82V3280
Address: 42H
Type: Read
Default Value: 00000000
Address: 43H
Type: Read
Default Value: X110X110
IN_FREQ_VAL
7 - 0
Bit
Bit
7
6
5
4
3
2
1
0
UE7
7
7
-
IN_FREQ_VALUE[7:0]
IN2_NO_ACTIVITY_ALARM
IN1_NO_ACTIVITY_ALARM
IN2_FREQ_HARD_ALARM
IN1_FREQ_HARD_ALARM
IN2_PH_LOCK_ALARM
IN1_PH_LOCK_ALARM
IN2_FREQ_HA
IN_FREQ_VAL
RD_ALARM
Name
Name
UE6
6
6
-
-
These bits represent a 2’s complement signed integer. If the value is multiplied by the value in the
FREQ_MON_FACTOR[3:0] bits (b3~0, 2EH), the frequency of an input clock with respect to the reference clock in ppm will
be gotten. The input clock is selected by the IN_FREQ_READ_CH[3:0] bits (b3~0, 41H).
The value in these bits is updated every 16 seconds, starting when an input clock is selected.
IN2_NO_ACTIV
IN_FREQ_VAL
ITY_ALARM
Reserved.
This bit indicates whether IN2 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN2 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN2 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period ( = TIME_OUT_VALUE[5:0] (b5~0, 08H) X
MULTI_FACTOR[1:0] (b7~6, 08H) in second ) which starts from when the alarm is raised.
Reserved.
This bit indicates whether IN1 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN1 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN1 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period ( = TIME_OUT_VALUE[5:0] (b5~0, 08H) X
MULTI_FACTOR[1:0] (b7~6, 08H) in second ) which starts from when the alarm is raised.
UE5
5
5
IN2_PH_LOCK
IN_FREQ_VAL
_ALARM
UE4
4
4
109
IN_FREQ_VAL
UE3
3
3
-
Description
Description
IN1_FREQ_HA
IN_FREQ_VAL
RD_ALARM
UE2
2
2
IN1_NO_ACTIV
IN_FREQ_VAL
ITY_ALARM
UE1
1
1
December 9, 2008
IN_FREQ_VAL
IN1_PH_LOCK
_ALARM
UE0
0
0
WAN PLL