IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 75

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

INTERRUPTS2_STS - Interrupt Status 2
Programming Information
IDT82V3280
Address: 0EH
Type: Read / Write
Default Value: 00111111
T0_OPERATING
5 - 0
Bit
7
6
_MODE
7
T0_OPERATING_MODE
T0_MAIN_REF_FAILED
T0_MAIN_REF_F
Name
INn
AILED
6
This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the
T0_DPLL_OPERATING_MODE[2:0] bits (b2~0, 52H) changes.
0: Has not switched. (default)
1: Has switched.
This bit is cleared by writing a ‘1’.
This bit indicates whether the T0 selected input clock has failed. The T0 selected input clock fails when its validity
changes from ‘valid’ to ‘invalid’; i.e., when there is a transition from ‘1’ to ‘0’ on the corresponding INn bit (4AH, 4BH).
0: Has not failed. (default)
1: Has failed.
This bit is cleared by writing a ‘1’.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn for T0
path, i.e., whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn bit (b5~0, 4BH). Here n
is any one of 14 to 9.
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
IN14
5
IN13
4
75
IN12
3
Description
IN11
2
IN10
1
December 9, 2008
IN9
0
WAN PLL