IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 132
IDT82V3280PFG
Manufacturer Part Number
IDT82V3280PFG
Description
IC PLL WAN SE STRATUM 2 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of IDT82V3280PFG
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
622.08MHz
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3280PFG
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V3280PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT82V3280PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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T4_DPLL_LOCKED_BW_DAMPING_CNFG - T4 DPLL Locked Bandwidth & Damping Factor Configuration
CURRENT_DPLL_FREQ[7:0]_STS - DPLL Current Frequency Status 1 *
CURRENT_DPLL_FREQ[15:8]_STS - DPLL Current Frequency Status 2 *
Programming Information
Address: 61H
Type: Read / Write
Default Value: 011XXX00
IDT82V3280
Address: 62H
Type: Read
Default Value: 00000000
Address: 63H
Type: Read
Default Value: 00000000
T4_DPLL_LOCK
ED_DAMPING2
CURRENT_DP
CURRENT_DP
LL_FREQ15
LL_FREQ7
7 - 5
4 - 2
1 - 0
7 - 0
7 - 0
Bit
Bit
Bit
7
7
7
T4_DPLL_LOCKED_DAMPING[2:0]
CURRENT_DPLL_FREQ[15:8] Refer to the description of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H).
CURRENT_DPLL_FREQ[7:0] Refer to the description of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H).
T4_DPLL_LOCKED_BW[1:0]
T4_DPLL_LOCK
ED_DAMPING1
CURRENT_DP
CURRENT_DP
LL_FREQ14
LL_FREQ6
Name
6
6
6
Name
Name
-
T4_DPLL_LOCK
CURRENT_DP
CURRENT_DP
ED_DAMPING0
LL_FREQ13
LL_FREQ5
5
5
5
These bits set the locked damping factor for T4 DPLL.
000: Reserved.
001: 1.2.
010: 2.5.
011: 5. (default)
100: 10.
101: 20.
110, 111: Reserved.
Reserved.
These bits set the locked bandwidth for T4 DPLL.
00: 18 Hz. (default)
01: 35 Hz.
10: 70 Hz.
11: 560 Hz.
CURRENT_DP
CURRENT_DP
LL_FREQ12
LL_FREQ4
4
4
4
-
132
CURRENT_DP
CURRENT_DP
LL_FREQ11
LL_FREQ3
3
3
3
-
Description
Description
Description
CURRENT_DP
CURRENT_DP
LL_FREQ10
LL_FREQ2
2
2
2
-
CURRENT_DP
CURRENT_DP
T4_DPLL_LOC
LL_FREQ1
LL_FREQ9
KED_BW1
1
1
1
December 9, 2008
CURRENT_DP
CURRENT_DP
T4_DPLL_LOC
LL_FREQ0
LL_FREQ8
KED_BW0
0
0
0
WAN PLL
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