ISL12026IBZ Intersil, ISL12026IBZ Datasheet - Page 10

• Manufacturer Part Number: ISL12026IBZ
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12026IBZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Clock Format: HH
• Clock Ic Type: RTC
• Interface Type: I2C, Serial
• Memory Configuration: 512 X 8
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
ADDR.
000D
000C
003F
0037
0036
0035
0034
0033
0032
0031
0030
0014
0013
0012
0010
000F
000E
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
0011
(EEPROM)
(EEPROM)
(EEPROM)
(SRAM)
Control
Alarm1
Alarm0
Status
TYPE
RTC
REG NAME
DWA1
MOA1
MNA1
DWA0
MOA0
MNA0
HRA1
HRA0
YRA1
DTA1
SCA1
YRA0
DTA0
SCA0
PWR
Y2K1
Y2K0
DTR
Y2K
ATR
DW
MO
INT
HR
MN
SR
YR
DT
SC
BL
10
EDW0
EDW1
EMO1
EMN1 A1M22
EMO0
EMN0 A0M22
EHR1
ESC1
EHR0
ESC0
EDT1
EDT0
SBIB
BAT
BP2
Y23
MIL
IM
0
0
0
0
0
0
0
0
0
0
7
Unused - Default = RTC Year value (No EEPROM) - Future expansion
Unused - Default = RTC Year value (No EEPROM) - Future expansion
A1S22
A0S22
AL1E
BSW
M22
BP1
AL1
Y22
S22
TABLE 2. CLOCK/CONTROL MEMORY MAP
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ISL12026, ISL12026A
A1Y2K21 A1Y2K20 A1Y2K13
A0Y2K21 A0Y2K20 A0Y2K13
A1M21
A0M21
A1D21
A1H21
A0D21
A0H21
Y2K21
A1S21
A0S21
ATR5
AL0E
D21
H21
M21
BP0
AL0
Y21
S21
5
0
0
0
0
0
0
0
0
A1M20
A0M20
Y2K20
A1G20
A1D20
A1H20
A1S20
A0G20
A0D20
A0H20
A0S20
OSCF
ATR4
FO1
G20
D20
H20
M20
Y20
S20
4
0
0
0
0
0
0
BIT
enabled for a match. See “Device Operation” on page 12
and “Application Section” on page 19 for more information.
Control Registers (Non-Volatile)
The Control Bits and Registers described in the following are
non-volatile.
BL Register
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will prevent
write operations to one of eight segments of the array. The
partitions are described in Table 3.
A1G13
A1M13
A0G13
A0M13
Y2K13
A1D13
A1H13
A1S13
A0D13
A0H13
A0S13
ATR3
M13
FO0
Y13
G13
D13
H13
S13
3
0
0
0
0
0
0
0
A1G12 A1G11
A1M12 A1M11
A0G12 A0G11
A0M12 A0M11
A1D12
A1H12
A1S12
A0D12
A0H12
A0S12
RWEL
DTR2
ATR2
DY2
M12
DY2
DY2
Y12
G12
D12
H12
S12
2
0
0
0
0
0
0
A1D11
A1H11
A1S11
A0D11
A0H11
A0S11
DTR1
ATR1
WEL
DY1
DY1
DY1
G11
D11
H11
M11
Y11
S11
1
0
0
0
0
0
0
A1Y2K10
A0Y2K10
A1G10
A1H10
A1M10
A0G10
A0H10
A0M10
Y2K10
A1D10
A1S10
A0D10
A0S10
RTCF
DTR0
ATR0
DY0
G10
M10
DY0
DY0
Y10
D10
H10
S10
0
0
0
0
RANGE
19/20
19/20
19/20
0-99
1-12
1-31
0-23
0-59
0-59
1-12
1-31
0-23
0-59
0-59
1-12
1-31
0-23
0-59
0-59
0-6
0-6
0-6
November 30, 2010
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