ISL12026IBZ Intersil, ISL12026IBZ Datasheet - Page 17

• Manufacturer Part Number: ISL12026IBZ
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12026IBZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Clock Format: HH
• Clock Ic Type: RTC
• Interface Type: I2C, Serial
• Memory Configuration: 512 X 8
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

individual register writes are not allowed. (Note: Prior to
writing to the CCR, the master must write a 02h, then 06h to
the status register in two preceding operations to enable the
write operation. See “Writing to the Clock/Control Registers”
on page 12).
After the receipt of each byte, the ISL12026 responds with
an acknowledge, and the address is internally incremented
by one. The address pointer remains at the last address byte
written. When the counter reaches the end of the page, it
“rolls over” and goes back to the first address on the same
page. This means that the master can write 16 bytes to a
memory array page or 8 bytes to a CCR section starting at
any location on that page. For example, if the master begins
writing at location 10 of the memory and loads 15 bytes, then
the first 6 bytes are written to addresses 10 through 15, and
the last 6 bytes are written to columns 0 through 5.
Afterwards, the address counter would point to location 6 on
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE SLAVE
SDA BUS
ADDRESS POINTER ENDS
6 BYTES
FIGURE 18. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10
ADDRESS = 5
AT ADDR = 5
S
A
R
T
T
1
17
ADDRESS
SLAVE
1
1
1
0
A
C
K
0 0 0 0 0 0 0
FIGURE 17. PAGE WRITE SEQUENCE
ADDRESS 1
ISL12026, ISL12026A
WORD
A
C
K
ADDRESS 0
WORD
the page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over-written by the new data, one byte at a
time. Refer to Figure 18. The master terminates the Data
Byte loading by issuing a stop condition, which causes the
ISL12026 to begin the non-volatile write cycle. As with the
byte write operation, all inputs are disabled until completion
of the internal write cycle. Refer to Figure 17 for the address,
acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must be sent
by the master after sending at least 1 full data byte and it’s
associated ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte + ACK is sent, then the
ISL12026 resets itself without performing the write. The
contents of the array are not affected.
ADDRESS
10
A
C
K
1 ≤ N ≤ 16 FOR EEPROM ARRAY
1 ≤ N ≤ 8 FOR CCR
DATA
(1)
6 BYTES
ADDRESS
15
DATA
(n)
A
C
K
November 30, 2010
O
S
T
P
FN8231.9