ISL12026IBZ Intersil, ISL12026IBZ Datasheet - Page 7

• Manufacturer Part Number: ISL12026IBZ
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12026IBZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Clock Format: HH
• Clock Ic Type: RTC
• Interface Type: I2C, Serial
• Memory Configuration: 512 X 8
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Typical Performance Curves
Description
The ISL12026 device is a Real Time Clock with clock/
calendar, two polled alarms with integrated 512x8 EEPROM,
oscillator compensation and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz crystal.
All compensation and trim components are integrated on the
chip. This eliminates several external discrete components
and a trim capacitor, saving board area and component cost.
The Real Time Clock keeps track of time with separate
registers for Hours, Minutes and Seconds. The Calendar has
separate registers for Date, Month, Year and Day-of-week.
The calendar is correct through 2099, with automatic leap
year correction.
The Dual Alarms can be set to any Clock/Calendar value for
a match. For instance, every minute, every Tuesday, or 5:23
AM on March 21. The alarms can be polled in the Status
Register or can provide a hardware interrupt (IRQ/F
Pin). There is a pulse mode for the alarms allowing for
repetitive alarm functionality.
The IRQ/F
frequency output of 1Hz, 4096Hz, or 32,768Hz or inactive.
The device offers a backup power input pin. This V
allows the device to be backed up by battery or SuperCap.
The entire ISL12026 device is fully operational from 2.7V to
5.5V and the clock/calendar portion of the ISL12026 device
remains fully operational down to 1.8V (Standby Mode).
The ISL12026 device provides 4k bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock™ allows a
safe, secure memory for critical user and configuration data,
while allowing a large user storage area.
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.8
OUT
2.3
pin may be software selected to provide a
FIGURE 5. I
2.8
3.3
7
V
DD3
DD
3.8
(V)
vs V
DD
4.3
(Continued)Temperature is +25°C unless otherwise specified.
4.8
ISL12026, ISL12026A
BAT
OUT
5.3
pin
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device. The input buffer on this pin is always active (not
gated). The pull-up resistor on this pin must use the same
voltage source as V
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It has an open drain output and may be wire
ORed with other open drain or open collector outputs. The
input buffer is always active (not gated).
This open drain output requires the use of a pull-up resistor.
The pull-up resistor on this pin must use the same voltage
source as V
output signal with the use of a slope controlled pull-down. The
circuit is designed to comply with 400kHz I
V
This input provides a backup supply voltage to the device.
V
supply fails. This pin can be connected to a battery, a
SuperCap or tied to ground if not used.
IRQ/F
This dual function pin can be used as an interrupt or
frequency output pin. The IRQ/F
the frequency out control bits of the INT register.
• Interrupt Mode. The pin provides an interrupt signal
• Frequency Output Mode. The pin outputs a clock signal
BAT
BAT
output. This signal notifies a host processor that an alarm
has occurred and requests action. It is an open drain
active low output.
which is related to the crystal frequency. The frequency
output is user selectable and enabled via the I
an open drain output.
-20
-40
80
60
40
20
supplies power to the device in the event the V
0
OUT
-32 -28 -24 -20 -16 -12 -8 -4
DD
(Interrupt Output/Frequency Output)
FIGURE 6. ΔF
. The output circuitry controls the fall time of the
DD
.
OUT
ATR SETTING
vs ATR SETTING
OUT
0
4
mode is selected via
8 12 16 20 24 28
2
C interface speed.
November 30, 2010
2
C bus. It is
DD
FN8231.9