STLC7550TQF7TR STMicroelectronics, STLC7550TQF7TR Datasheet
STLC7550TQF7TR
Specifications of STLC7550TQF7TR
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STLC7550TQF7TR Summary of contents
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Features ■ General purpose signal processing Analog Front End (AFE) ■ Targeted for V.34bis Modem and 56Kbps Modem applications 16-BIT oversampling Σ∆ A/D and D/A ■ converters ■ 83dB signal to noise ratio for sampling frequency up to 9.6kHz @ ...
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Content Content 1 Pins description & Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 ...
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STLC7550 1 Pins description & Block diagram Figure 1. Pin connection (top view) Table 1. Pin list Pin # ...
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Pins description & Block diagram Table 1. Pin list (continued) Pin # Note obtain published performance, the analog V respect to Analog Ground ...
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STLC7550 Digital Ground (DGND) This pin is the ground for DAC and ADC internal digital circuitry. 1.1.2 Host interface (10 pins) Data In (DIN) In Data Mode, the data word is the input of the DAC channel. In software, the ...
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Pins description & Block diagram Master/Slave Control (M/S) When M/S is high, the device is in master mode and Fs is generated internally. When M/S is low, the device is in slave mode and Fs must be generated externally. Master ...
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STLC7550 than two times the sampling frequency (FS), so that the combined frequency response of both the internal and external filters is flat in the passband. The attenuator of the last output stage can be programmed to 0dB, 6dB or ...
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Functional description 2 Functional description 2.1 Transmit D/A section The functions included in the Tx D/A section are detailed hereafter. 16-bit 2’s complement data format is used in the DAC channel. 2.1.1 Transmit Low Pass Filters The transmit low pass ...
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STLC7550 The IIR is a cascade of 5 biquads. It provides the low-pass filtering needed to remove the noise remaining above half the sampling frequency. The output of the IIR will be processed by the DSP. 2.3 Clock generator The ...
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Functional description Figure 3. Clock Block Diagram XTALIN (MCLK) 2.4 Modes of operation Thanks to MCM and M/S programmation pins we can get the following configuration. Configuration 1 : MCM = 1, M The STLC7550 is in master ...
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STLC7550 Figure 5. Configuration 2 Figure 6. Configuration 3 (7546 mode) Configuration 5 : MCM = 1, M (master codec) MCM = 0, M (slave codec) This is dual codec application. The master codec has his ...
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Functional description Figure 8. Configuration 5 2.5 Host interface The Host interface consist of the shift clock, the frame synchronization signal, the ADCchannel data output, and the DAC-channel data input. Two modes of serial transfer are available : – First ...
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STLC7550 Table 3. Mode selection (continued) HC1 HC0 LSB Figure 9. Data Mode FS SCLK TxDI - TxDO - HC1, HC0 Figure 10. Mixed Mode FS SCLK TxDI TxDO HC1, HC0 Note : In ...
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Functional description Table 4. Bits Assignment (continued) Bits Name TEST2 15 TEST3 Table 5. Aux/Main Input D1 ...
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STLC7550 Table 7. Oversampling Ratio (continued Table 8. Transmit Attenuation Table 9. Q Divider Clock Generator D11 D10 0 0 ...
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Electrical Specifications 3 Electrical Specifications Unless otherwise noted, Electrical Characteristics are specified over the operating range. Typical values are given for V MCLK = 1.536MHz and oversampling ratio = 160. 3.1 Absolute maximum ratings Table 12. Absolute Maximum Ratings (referenced ...
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STLC7550 Table 13. Nominal DC Characteristics (continued ± 5%, GND = 0V Symbol I Input Current High Level Output Voltage ( Low Level Output Voltage (I OL ...
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Electrical Specifications Table 14. Nominal AC Electrical Characteristics (continued) (Reference level V Output load = 50pF unless otherwise) Symbol N° 3 SCLK Width High 4 SCLK Rise Time 5 SCLK Fall Time 6 FS Setup 7 FS Hold 8 DIN ...
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STLC7550 3.4 Transmit Characteristics 3.4.1 Performance of the Tx channel Table 15. Performance of the Tx channel Typical values are given for AV clock MCLK = 1.536MHz, differential mode and oversampling ratio = 160. Measurement band = 100Hz to 0.425 ...
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Typical application 4 Typical application Figure 12. Line Interface - Differential Duplexor OUT+ OUT- IN+ IN- All capacitor, resistor and impedance values are provided for indication only. These values must be readjusted according to line transformer characteristics and also telecommunication ...
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STLC7550 5 Definition and Terminology Data Transfer Interval Signal Data Data Mode Control Mode Frame Sync. Frame Sync and Sampling Period ADC Channel DAC Channel OverSampling Ratio Resolution Dynamic Range Signal-to- (Noise+Distortion) Crosstalk Power Supply Rejection Ratio The time during ...
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Package information 6 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the ...
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STLC7550 7 Revision history Table 17. Document revision history Date 14-Jan-2004 06-Feb-2006 Revision 8 Initial release. Removed the TQFP44 package and the respective ordering part number. 9 Inserted the new part number E-STLC7550TQF7 (ECOPACK). Rev 9 Revision history Changes 23/24 ...
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