SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 196

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

196
Index 4Ch-4Fh
Index 50h
Index 51h
Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued)
31:0
Bit
2:0
7:4
3:0
7
6
5
4
3
Description
Top of System Memory. Highest address in system used to determine active decode for external PCI mastered memory
cycles.
If an external PCI master requests a memory address below the value programmed in this register, the cycle is transferred
from the external PCI bus interface to the Fast-PCI interface for servicing by the GX1 module.
Note:
PIT Software Reset.
0: Disable.
1: Enable.
PIT Counter 1.
0: Forces Counter 1 output (OUT1) to zero.
1: Allows Counter 1 output (OUT1) to pass to the Port 061h[4].
PIT Counter 1 Enable.
0: Sets GATE1 input low.
1: Sets GATE1 input high.
PIT Counter 0.
0: Forces Counter 0 output (OUT0) to zero.
1: Allows Counter 0 output (OUT0) to pass to IRQ0.
PIT Counter 0 Enable.
0: Sets GATE0 input low.
1: Sets GATE0 input high.
ISA Clock Divisor. Determines the divisor of the PCI clock used to make the ISA clock, which is typically programmed for
approximately 8 MHz:
000: Divide by 1
001: Divide by 2
010: Divide by 3
011: Divide by 4
If PCI clock = 25 MHz, use setting of 010 (divide by 3).
If PCI clock = 30 or 33 MHz, use a setting of 011 (divide by 4).
8-Bit I/O Recovery. These bits determine the number of ISA bus clocks between back-to-back 8-bit I/O read cycles. This
count is in addition to a preset one-clock delay built into the controller.
0000: 1 PCI clock
0001: 2 PCI clocks
:::
:::
:::
1111: 16 PCI clocks
16-Bit I/O Recovery. These bits determine the number of ISA bus clocks between back-to-back 16-bit I/O cycles. This count
is in addition to a preset one-clock delay built into the controller.
0000: 1 PCI clock
0001: 2 PCI clocks
:::
:::
:::
1111: 16 PCI clocks
The four least significant bits must be set to 1100.
32579B
ISA I/O Recovery Control Register (R/W)
PIT Control/ISA CLK Divider (R/W)
Top of System Memory (R/W)
100: Divide by 5
101: Divide by 6
110: Divide by 7
111: Divide by 8
Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0
AMD Geode™ SC1200/SC1201 Processor Data Book
Reset Value: FFFFFFFFh
Reset Value: 7Bh
Reset Value: 40h