SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 309

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

Core Logic Module - ISA Legacy Register Space
AMD Geode™ SC1200/SC1201 Processor Data Book
I/O Port 4D1h
Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides the setting for bits 7:6 and 4:1 in this register.
Bit
2:0
7
6
5
4
3
2
1
0
2. Bits [7:6] and [4:1] in this register are used to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive
Description
Reserved. Must be set to 0.
IRQ15 Edge or Level Sensitive Select. Selects PIC IRQ15 sensitivity configuration.
0: Edge.
1: Level.
IRQ14 Edge or Level Sensitive Select. Selects PIC IRQ14 sensitivity configuration.
0: Edge.
1: Level.
Reserved. Must be set to 0.
IRQ12 Edge or Level Sensitive Select. Selects PIC IRQ12 sensitivity configuration.
0: Edge.
1: Level.
IRQ11 Edge or Level Sensitive Select. Selects PIC IRQ11 sensitivity configuration.
0: Edge.
1: Level.
IRQ10 Edge or Level Sensitive Select. Selects PIC IRQ10 sensitivity configuration.
0: Edge.
1: Level.
IRQ9 Edge or Level Sensitive Select. Selects PIC IRQ9 sensitivity configuration.
0: Edge.
1: Level.
Reserved. Must be set to 0.
(shared).
Table 6-49. Miscellaneous Registers (Continued)
Interrupt Edge/Level Select Register 2 (R/W)
32579B
Reset Value: 00h
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