S2065A Applied Micro Circuits Corporation, S2065A Datasheet - Page 8

• Manufacturer Part Number: S2065A
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S2065A

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

A special input is provided to simplify the generation
of the K28.5 character. An SOFx input is provided
for each channel. When SOF is asserted, the K28.5
character is generated regardless of the data on the
parallel input. The K28.5 character can be of either
positive or negative parity, depending on the current
running disparity. When the chip is in CHANNEL
LOCK mode, assertion of SOFA causes the K28.5 to
be generated on all four serial data streams, SOFC
is ignored. When SOFD is asserted during CHAN-
NEL LOCK mode, this resets the Channel Lock
State Machine. Table 3 shows the mapping of the
8B/10B characters representation. Data is transmit-
ted bit “a” or DIN[0] first.
8
S2065
Table 2. K Character Generation (SOFx = 0)
C
h
K
K
K
K
K
K
K
K
K
K
K
K
a
2
2
2
2
2
2
2
2
2
2
2
3
a r
K
8
8
8
8
8
8
8
8
3
7
9
0
0 .
1 .
2 .
3 .
4 .
5 .
6 .
7 .
7 .
7 .
7 .
7 .
t c
r e
0
0
0
0
1
1
1
1
1
1
1
1
D
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
N I
1
1
1
1
1
1
1
1
1
1
1
1
[
: 7
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
] 0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
1
1
0
K
G
1
1
1
1
1
1
1
1
1
1
1
1
E
N
QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O
C
1
1
1
1
1
1
1
1
0
0
0
1
a
1
1
1
1
1
1
1
1
0
0
1
0
r u
b
0
0
0
0
0
0
0
0
0
1
0
0
c
0
0
0
0
0
0
0
0
1
0
0
0
e r
d
0
0
0
0
0
0
0
0
0
0
0
0
t n
i e
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
0
1
0
0
0
0
0
g f
R
In addition to data and K characters, the S2065 can
also generate a unique sync sequence consisting of
16 consecutive K28.5 characters. This event is initi-
ated by the simultaneous assertion of KGENx and
SOFx for one clock period. The SOFx and KGENx
inputs should be held low until the sync sequence has
completed. The sync sequence may start with either a
positive or negative parity K28.5. (Depending on the
current running disparity.) The parity of the second
and third K28.5 are inverse with respect to a valid 8B/
10B sequence. Parity of the remaining K28.5 alter-
nate in accordance with the 8B/10B coding standard.
Thus, the parity of the K28.5 pattern consists of + + - -
+ - + - + - + - + - + - or - - + + - + - + - + - + - + - +.
Tables 4 and 4a show the transmitter control signals
for both Normal and Channel Lock mode.
0
1
0
1
1
1
0
1
1
1
1
1
D
j h
1
1
1
0
0
0
0
1
1
1
1
1
+
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
C
a
0
0
0
0
0
0
0
0
1
1
0
1
r u
b
1
1
1
1
1
1
1
1
1
0
1
1
c
1
1
1
1
1
1
1
1
0
1
1
1
e r
d
1
1
1
1
1
1
1
1
1
1
1
1
i e
t n
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
g f
R
1
0
1
0
0
0
1
0
0
0
0
0
j h
D
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
-
October 13, 2000 / Revision G
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