W66910CD Winbond Electronics, W66910CD Datasheet - Page 3

• Manufacturer Part Number: W66910CD
• Manufacturer: Winbond Electronics

Specifications of W66910CD

• Lead Free Status / Rohs Status: Not Compliant

TABLE OF CONTENTS
1. GENERAL DESCRIPTION................................................................................................................................................. 8
2. FEATURES............................................................................................................................................................................ 8
3. PIN CONFIGURATION ..................................................................................................................................................... 9
4. PIN DESCRIPTION........................................................................................................................................................... 11
5. SYSTEM DIAGRAM AND APPLICATIONS................................................................................................................ 13
6. BLOCK DIAGRAM ........................................................................................................................................................... 14
7. FUNCTIONAL DESCRIPTIONS..................................................................................................................................... 15
8. REGISTER DESCRIPTIONS ............................................................................................................................................. 42
7.1 M
7.2 L
7.3 S
7.4 B C
7.5 PCM P
7.6 D C
7.7 B C
7.8 GCI M
7.9 8-
7.10 P
7.2.1 S/T Interface Transmitter/Receiver ............................................................................................................................ 16
7.2.2 Receiver Clock Recovery And Timing Generation...................................................................................................... 20
7.2.3 Layer 1 Activation/Deactivation ................................................................................................................................ 20
7.2.4 D Channel Access Control......................................................................................................................................... 26
7.2.5 Frame Alignment ....................................................................................................................................................... 26
7.2.6 Multiframe Synchronization....................................................................................................................................... 28
7.2.7 Test Functions ........................................................................................................................................................... 29
7.6.1 D Channel Message Transfer Modes.......................................................................................................................... 34
7.6.2 Reception of Frames in D Channel ............................................................................................................................ 34
7.6.3 Transmission of Frames in D Channel ....................................................................................................................... 35
7.7.1 Reception of Frames in B Channel
7.7.2 Transmission of Frames in B Channel........................................................................................................................ 37
7.8.1 GCI Mode C/I0 Channel Handling ............................................................................................................................ 39
7.8.2 GCI Mode Monitor Channel Handling....................................................................................................................... 39
7.2.3.1 States Descriptions And Command/Indication Codes .......................................................................................... 20
7.2.3.2 State Transition Diagrams................................................................................................................................... 22
7.2.5.1 FAinfA_1fr ......................................................................................................................................................... 27
7.2.5.2 FAinfB_1fr ......................................................................................................................................................... 27
7.2.5.3 FAinfD_1fr ......................................................................................................................................................... 27
7.2.5.4 FAinfA_kfr ......................................................................................................................................................... 27
7.2.5.5 FAinfB_kfr ......................................................................................................................................................... 27
7.2.5.6 FAinfD_kfr ......................................................................................................................................................... 28
7.2.5.7 Faregain.............................................................................................................................................................. 28
ERIAL
AYER
BIT
AIN
ERIPHERAL
HANNEL
HANNEL
HANNEL
M
B
ODE
1 F
ORT
I
LOCK
ICROPROSESSOR
NTERFACE
UNCTIONS
S
....................................................................................................................................................................... 33
S
HDLC C
HDLC C
ERIAL
F
WITCHING
C
UNCTIONS
ONTROL
B
I
NTERFACE
US
D
ONTROLLER
ONTROLLER
ESCRIPTIONS
..................................................................................................................................................... 31
..................................................................................................................................................... 40
I
.................................................................................................................................................... 31
................................................................................................................................................... 15
NTERFACE
B
US
...................................................................................................................................... 33
...................................................................................................................................... 36
.................................................................................................................................... 38
................................................................................................................................... 16
C
IRCUIT
....................................................................................................................... 36
...................................................................................................................... 40
-3 -
W66910 PCI ISDN S/T-Controller
Publication Release Date:
Data Sheet
Revision 1.0
Feb,2001