W66910CD Winbond Electronics, W66910CD Datasheet - Page 47

• Manufacturer Part Number: W66910CD
• Manufacturer: Winbond Electronics

Specifications of W66910CD

• Lead Free Status / Rohs Status: Not Compliant

Data Sheet
W66910 PCI ISDN S/T-Controller
After writing this register, STT1 bit in D_CMDR register must be set to start the timer. This register can be read only after the
timer has been started. The read value indicates the timer's current count value. In case layer 1 is not activated, a C/I command
"ECK" must be issued in addition to the STT1 command to start the timer.
The timer is stopped when it expires (T1MD=0) or TIMR1 register is re-written.
8.1.6 Interrupt Status Register
ISTA
Read_clear
Address 05H
Value after reset : 00H
7
6
5
4
3
2
1
0
D_RMR
D_RME
D_XFR
XINT1
XINT0
D_EXI
B1_EXI
B2_EXI
D_RMR D_ch Receive Message Ready
A 64-byte data is available in the D_RFIFO. The frame is not complete yet.
D_RME D_ch Receive Message End
The last part of a frame with length > 64 bytes or a whole frame with length
64 bytes has been received. The whole frame
length is obtained from D_RBCH + D_RBCL registers. The length of data in the D_RFIFO equals:
data length = RBC5-0 if RBC5-0
0
data length = 64 if RBC5-0 =0
D_XFR D_ch Transmit FIFO Ready
This bit indicates that the transmit FIFO is ready to accept data. Up to 64 bytes of data can be written into the D_XFIFO.
An D_XFR interrupt is generated in the following cases :
- After an XMS command, when 64 bytes of XFIFO is empty
- After an XMS together with an XME command is issued, when the whole frame has been transmitted
- After an XRST command
- After hardware reset
XINT1 XINTIN1 Interrupt
This bit indicates that level change occurs at XINTIN1 pin. Both positive and negative edges will cause an interrupt.
XINT0 XINTIN1 Interrupt
This bit indicates that level change occurs at XINTIN0 pin. Both positive and negative edges will cause an interrupt.
D_EXI D_ch Extended Interrupt
This bit indicates that at least one interrupt bit has been set in D_EXIR register.
B1_EXI B1_ch Extended Interrupt
This bit indicates that at least one interrupt bit has been set in B1_EXIR register.
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Publication Release Date:
Feb,2001
Revision 1.0